// (C) 2022 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other 
// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
// files), and any associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License Subscription 
// Agreement, Intel FPGA IP License Agreement, or other applicable 
// license agreement, including, without limitation, that your use is for the 
// sole purpose of programming logic devices manufactured by Intel and sold by 
// Intel or its authorized distributors.  Please refer to the applicable 
// agreement for further details.

`timescale 1ns / 1ps
`include "mainfpga_version.vh"

module mainfpga_top
   (
    
    /**********************************************************************/
    /*                       MAIN CLOCKS AND RESETS                       */
    /**********************************************************************/

    input  CLK_25M_OSC_MAIN_FPGA_LVC3,
    input  PWRGD_P1V2_MAX10_AUX_PLD_R_LVC3,
 
    /**********************************************************************/

    input  FM_CPU0_PROC_ID0,
    input  FM_CPU0_PROC_ID1,

    input  FM_CPU1_PROC_ID1,
    input  FM_CPU1_PROC_ID0,

    input  FM_CPU0_PKGID0,
    input  FM_CPU0_PKGID1,
    input  FM_CPU0_PKGID2,

    input  FM_CPU1_PKGID0,
    input  FM_CPU1_PKGID1,
    input  FM_CPU1_PKGID2,

    input  FM_BOARD_REV_ID0,
    input  FM_BOARD_REV_ID1,
    input  FM_BOARD_REV_ID2,

    input  FM_BOARD_SKU_ID0,
    input  FM_BOARD_SKU_ID1,
    input  FM_BOARD_SKU_ID2,
    input  FM_BOARD_SKU_ID3,
    input  FM_BOARD_SKU_ID4,
    input  FM_BOARD_SKU_ID5,


    input  M_AB_CPU0_RESET_LVC1_N,
    input  M_CD_CPU0_RESET_LVC1_N,
    input  M_EF_CPU0_RESET_LVC1_N,
    input  M_GH_CPU0_RESET_LVC1_N,

    output M_AB_CPU0_FPGA_RESET_R_LVC1_N,
    output M_CD_CPU0_FPGA_RESET_R_LVC1_N,
    output M_EF_CPU0_FPGA_RESET_R_LVC1_N,
    output M_GH_CPU0_FPGA_RESET_R_LVC1_N,
 
    input  M_AB_CPU1_RESET_LVC1_N,
    input  M_CD_CPU1_RESET_LVC1_N,
    input  M_EF_CPU1_RESET_LVC1_N,
    input  M_GH_CPU1_RESET_LVC1_N,

    output M_AB_CPU1_FPGA_RESET_R_LVC1_N,
    output M_CD_CPU1_FPGA_RESET_R_LVC1_N,
    output M_EF_CPU1_FPGA_RESET_R_LVC1_N,
    output M_GH_CPU1_FPGA_RESET_R_LVC1_N,

    output PWRGD_DRAMPWRGD_CPU1_AB_R_LVC1, 
    output PWRGD_DRAMPWRGD_CPU1_CD_R_LVC1,
    output PWRGD_DRAMPWRGD_CPU1_EF_R_LVC1,
    output PWRGD_DRAMPWRGD_CPU1_GH_R_LVC1,

    output PWRGD_DRAMPWRGD_CPU0_AB_R_LVC1, 
    output PWRGD_DRAMPWRGD_CPU0_CD_R_LVC1,
    output PWRGD_DRAMPWRGD_CPU0_EF_R_LVC1,
    output PWRGD_DRAMPWRGD_CPU0_GH_R_LVC1,
 
    output H_CPU0_NMI_LVC1_FPGA_R,
 
    input  H_CPU0_MEMHOT_OUT_LVC1_FPGA_N,
    output H_CPU0_MEMHOT_IN_LVC1_R_N,
 
    output H_CPU0_BMC_TRUSTED_LVC1_N,
    input  H_CPU0_MON_FAIL_PLD_LVC1_N,
 
    inout  FM_CPU0_GPIO0_RSVD_LVC1,

    inout  FM_CPU0_GPIO4_EAF_BMC_SAFS_SEL_LVC1,


    output PWRGD_CPU0_FPGA_LVC1,

    output PWRGD_CPU0_S0_PWROK_LVC1_R,
    output RST_CPU0_LVC1_R_N,

    input  H_CPU0_ERR0_FPGA_LVC1_R_N,
    input  H_CPU0_ERR1_FPGA_LVC1_R_N,
    input  H_CPU0_ERR2_FPGA_LVC1_R_N,
 
    output H_CPU0_PROCHOT_LVC1_R_N,
    input  H_CPU1_CATERR_LVC1_R2_N,
    output H_CPU0_BMCINIT_LVC1_R,
 
    input  H_CPU1_MEMHOT_OUT_LVC1_R2_N,
 
    output H_CPU1_MEMHOT_IN_LVC1_R_N,

    output H_CPU1_BMCINIT_LVC1_R,
    inout  FM_CPU1_TIMED_GPIO0_LVC1,

    input  FM_CPU1_GPIO4_EAF_BMC_SAFS_SEL_LVC1,
    inout  FM_CPU1_FRMAGENT_LVC1,
    input  H_CPU0_RMCA_LVC1_R2_N,


    input  H_CPU0_MEMTRIP_LVC1_FPGA_N,
    output H_CPU1_NMI_LVC1,
    
    input  PWRGD_P1V0_AUX,
    input  PWRGD_P1V1_AUX,
 
    input  H_CPU1_MON_FAIL_PLD_LVC1_N,
    inout  FM_CPU1_TIMED_GPIO1_LVC1,
    input  H_CPU0_CATERR_LVC1_R2_N,
    input  H_CPU0_THERMTRIP_FPGA_LVC1_R_N,
    input  H_CPU1_MEMTRIP_LVC1_R2_N,
    inout  FM_CPU0_TIMED_GPIO1_LVC1,
    output FM_CPU1_SOCKET_ID0_LVC1,
    inout  FM_CPU0_TIMED_GPIO0_LVC1,
    inout  FM_CPU1_GPIO0_PARTITION_ID0_LVC1,
    input  H_CPU1_ERR2_FPGA_LVC1_N,
    input  H_CPU1_RMCA_LVC1_R2_N,
    input  H_CPU1_ERR0_FPGA_LVC1_N,
    output H_CPU1_PROCHOT_LVC1_R_N,
    input  H_CPU1_ERR1_FPGA_LVC1_N,
    output PWRGD_CPU1_FPGA_LVC1,
    output RST_CPU1_LVC1_R_N,
    output PWRGD_CPU1_S0_PWROK_LVC1_R,
    input  H_CPU1_THERMTRIP_LVC1_R2_N,
    output FM_P3V3_LVC25_EN,
    input  IRQ_CPU0_VRHOT_LVC25_N,
    input  FM_CPU0_ADR_EXT_TRIGGER_LVC25_N,
    input  FM_RST_PERST_BIT1_LVC25,
    input  FM_RST_BTN_CPU1_LVC25_N,
    input  PWRGD_PVCCD0_HV_CPU0_LVC25_PWRGD,
    output FM_TS3DS10224_ENB_LVC25_OD,
    input  PWRGD_PVCCD1_HV_CPU0_LVC25_PWRGD,
    input  PWRGD_PVNN_MAIN_CPU0_LVC25_PWRGD,
    input  PWRGD_PVCCFA_EHV_CPU0_LVC25_PWRGD,
    input  PWRGD_PVCCINFAON_CPU0_LVC25_PWRGD,
    input  PWRGD_PVCCIN_CPU0_LVC25_PWRGD,
    output FM_PVCCD_HV_CPU0_EN_R_LVC25,
    input  IRQ_CPU0_MEM_VRHOT_LVC25_N,
    output FM_PVCCIN_CPU0_R_LVC25_EN,
    output FM_PVCCFA_EHV_CPU0_R_LVC25_EN,
    input  FM_BMCINIT_DISABLE_LVC25_N,
    input  PWRGD_PVCCFA_EHV_FIVRA_CPU0_LVC25,
    input  FM_PWR_BTN_CPU1_LVC25_N,
    input  PWRGD_PVCCD0_HV_CPU1_LVC25_PWRGD,
    output FM_PVCCFA_EHV_FIVRA_CPU0_R_LVC25_EN,

    input  FM_PASSWORD_CLEAR_LVC25_N,
    input  LVDS_LVC25_RX_DP,
    input  FM_PARTITION_SEL_HDR_LVC25, 
    output FM_PVNN_AUX_CPU0_EN_R_LVC25,
    input  IRQ_CPU1_MEM_VRHOT_LVC25_N,
    output FM_TS3DS10224_ENA_LVC25_OD,

    input  FM_CPU1_ADR_EXT_TRIGGER_LVC25_N,
    input  PWRGD_P3V3_LVC25_PWRGD,
    input  PWRGD_PVCCIN_CPU1_LVC25_PWRGD,

    output FM_PVCCINFAON_CPU0_R_LVC25_EN,
    output LVDS_LVC25_TX_DP,
    input  PWRGD_PVCCD1_HV_CPU1_LVC25_PWRGD,

    input  IRQ_CPU1_VRHOT_LVC25_N,
    input  LVDS_LVC25_CLK_RX_DP,
    input  FM_PFR_POSTCODE_SEL_LVC25_N,
    input  PWRGD_PVCCFA_EHV_FIVRA_CPU1_LVC25_PWRGD,
    input  FM_RST_PERST_BIT0_LVC25,
    input  PWRGD_PVCCFA_EHV_CPU1_LVC25_PWRGD,

    input  PWRGD_PVNN_MAIN_CPU1_LVC25_PWRGD,
    output LVDS_LVC25_CLK_TX_DP,
    input  PWRGD_PVCCINFAON_CPU1_LVC25_PWRGD,
    inout  SMB_PEHPCPU0_LVC3_FPGA_SDA,
    output FM_OCP_NIC_AUX_PWR_LVC3_R_EN,
    output FM_S3M_CPU0_CPLD_CONFIG_LVC3_N,
    output FM_PLD_OCP_NIC_RBT_ISOLATE_LVC3_N,
    input  SGPIO_IDV_DOUT_R_LVC3,
    output FM_GPIO_XDP_SKT_SEL_LVC3,
    output FM_OCP_NIC_MAIN_PWR_LVC3_R_EN,
    inout  SMB_PMBUS1_LVC3_SDA,
    input  SMB_PEHPCPU0_LVC3_FPGA_SCL,
    inout  SMB_PMBUS2_LVC3_SCL,
    inout  SMB_PMBUS1_LVC3_SCL,
    inout  SMB_PMBUS2_LVC3_SDA,
    output SGPIO_IDV_DIN_R_LVC3,
    input  SGPIO_IDV_LD_LVC3_R_N,
    input  FM_CPU0_SKTOCC_LVT3_PLD_N,
    input  FM_S3M_CPU1_CPLD_CRC_ERROR_LVC3,
    input  PWRGD_PS_PWROK_R2,
    input  FM_S3M_CPU0_CPLD_CRC_ERROR_LVC3,
    input  IRQ_CPU1_WAKE_LVC3_R_N,
    output FM_S3M_CPU1_CPLD_CONFIG_LVC3_N,
    input  FP_RST_BTN_N,
    input  FP_ID_BTN_LVC3_N,
    input  FP_PWR_BTN_N,
    output FP_LED_STATUS_GREEN_N,
    input  FM_CPU1_SKTOCC_LVT3_PLD_N,
    input  FM_CPU1_PE3_OCP_NIC_NVME14_PRSTN0_N,
    input  SGPIO_IDV_CLK_R_LVC3,
    input  FP_NMI_BTN_N,
    input  FM_SCM_PRSNT0_LVC3_N,
    output FM_P5V_EN,
    inout  RST_CPU1_RTCRST_PLD_R_N,
    inout  RST_CPU0_RTCRST_PLD_R_N,
    output FP_LED_STATUS_AMBER_N,
    input  IRQ_CPU0_WAKE_LVC3_R_N,
    input  FM_1200VA_OC,
    inout  FM_CPU0_EDSFFX4_EXPCARD_IO0_LVC3_R,
    output FP_ID_LED_N,
    input  FM_DBP_POD_PRSNT_N,
    output FM_PWR_LED_R_N,
    input  PWRGD_OCP_NIC_PWRGD,

    output FM_PS_EN_PLD_R_LVC3,

    output FM_CK440Q_SSC0_R_LVC3,

    output FM_PVNN_AUX_CPU1_LVC3_R_EN,
    output FM_PVCCFA_EHV_CPU1_LVC3_R_EN,
    output FM_PVCCD_HV_CPU1_LVC3_R_EN,
    inout  FM_CPU0_EDSFFX4_LED_LVC3,
    output FM_DIMM_PCIE_CPU1_SW_P12V_LVC3_R_EN,
    output FM_DUAL_PARTITION_LVC3_N,
    output FM_PARTITION_SEL_LVC3,
    inout  SMB_HOST_MAINFPGA_LVC3_SDA,
    input  FM_ASD_EN_DET_LVC3,
    inout  SMB_HOST_MAINFPGA_LVC3_SCL,
    inout  FM_CPU0_EDSFFX4_PWRDIS_LVC3,
    output FM_DUAL_PARTITION_QS_LVC3_N,
    inout  FM_CPU0_EDSFFX4_PRSNT0_LVC3_N,
    output FM_PLD_CLKS_DEV_LVC3_R_EN,
    inout  FM_BMC_CPU_FBRK_OUT_LVC3_N,
    inout  SMB_THERMAL_SENSOR_LVC3_SDA,
    output FM_PVCCINFAON_CPU1_LVC3_R_EN,
    output RST_PLD_PCIE_CPU1_DEV_PERST_LVC3_R_N,
    output FM_DIMM_PCIE_CPU0_SW_P12V_LVC3_R_EN,
    inout  SMB_THERMAL_SENSOR_LVC3_SCL,
    inout  PWRGD_FAIL_CPU1_AB_PLD_LVC3,
    inout  PWRGD_FAIL_CPU1_EF_PLD_LVC3,
    output FM_PECI_SEL_1_LVC3_N,
    inout  SMB_CPLD_UPDATE_STBY_LVC3_SCL,
    input  IRQ_SML1_PMBUS_PLD_ALERT_LVC3_N,
    input  FM_SERIAL_BOOT,
    output FM_DBP_JTAG_MUX_CPU1_LVC3_R_EN,
    inout  SMB_CPLD_UPDATE_STBY_LVC3_SDA,
    output FM_CK440Q_SSC1_R_LVC3,
    inout  SMB_CHASSIS_SENSOR_LVC3_SDA,
    output FM_PECI_SEL_0_LVC3_N,
    inout  SMB_PIROM_SDA,
    inout  PWRGD_FAIL_CPU0_GH_PLD_LVC3,
    inout  PWRGD_FAIL_CPU1_GH_PLD_LVC3,
    inout  PWRGD_FAIL_CPU0_EF_PLD_LVC3,
    inout  PWRGD_FAIL_CPU1_CD_PLD_LVC3,
    output FM_DBP_JTAG_MUX_CPU0_LVC3_R_EN,
    inout  SMB_CHASSIS_SENSOR_LVC3_SCL,
    input  SMB_PCIE_LVC3_SCL,
    inout  SMB_DEBUG_MPLD_LVC3_SDA,
    output FM_CPU1_PVCC3V3_AUX_EN_LVC3_R,
    inout  SMB_DEBUG_MPLD_LVC3_SCL,
    output FM_SPD_SWITCH_CTRL_LVC3_N,
    output reg FM_DBG_AUX_LVC3_PWRGD,
    output FM_CPU0_EDSFFX4_LED_LVC3_EN,
    output FM_PVCCFA_EHV_FIVRA_CPU1_LVC3_R_EN,
    inout  PWRGD_FAIL_CPU0_CD_PLD_LVC3,
    output FM_AUX_SW_LVC3_EN,
    inout  PWRGD_FAIL_CPU0_AB_PLD_LVC3,
    inout  SMB_PIROM_SCL,
    output RST_PLD_PCIE_CPU0_DEV_PERST_LVC3_R_N,
    inout  SMB_PCIE_LVC3_SDA,
    input  FM_CPU1_ADR_COMPLETE_LVC18,
    input  FM_CPU1_SLPS3_LVC18_N,
    inout FM_CPU1_ADR_TRIGGER_LVC18_N,
    input  RST_CPU0_PLTRST_SYNC_LVC18_N,
    output FM_CPU1_S5_PWR_RETAINED_R,
    output FM_CPU1_PWRBTN_LVC18_R_N,
    output FM_CPU0_S5_PWR_RETAINED_FPGA_R,
    input  UART_CPU1_TXD_LVC18_R3,
    output RST_CPU1_RSTBTN_LVC18_R_N,
    inout  ESPI_CPU1_IO0_FPGA_R_LVC18,

    input  UART_CPU0_CTS_LVC18_R3,
    
    output IRQ_ESPI_CPU1_ALERT1_FPGA_R_LVC18_N,
    input  FM_CPU0_SLPS4_FPGA_R_LVC18_N,
    input  ESPI_CPU1_CS1_FPGA_R_LVC18_N,
    input  FM_CPU0_ADR_COMPLETE_FPGA_LVC18,
    input  RST_ESPI_CPU1_FPGA_R_LVC18_N,
    output RST_CPU0_RSTBTN_FPGA_LVC18_R_N,
    input  UART_CPU0_RTS_LVC18_R3,
    output PWRGD_CPU1_PLT_AUX_PWRGD_FPGA_LVC18,
    inout  ESPI_CPU0_IO3_FPGA_R_LVC18,
    output IRQ_CPU0_WAKE_LVC18_R_N,
    inout  ESPI_CPU0_IO2_FPGA_R_LVC18,
    output SGPIO_MAIN_MOD_FPGA_DIN_R_LVC18,

    input  UART_CPU0_RXD_LVC18_R3,
    
    output PWRGD_CPU0_PLT_AUX_PWRGD_FPGA_LVC18_R,
    inout  ESPI_CPU0_IO1_FPGA_R_LVC18,
    input  RST_CPU1_PLTRST_SYNC_LVC18_N,
    input  UART_CPU0_TXD_LVC18_R3,
    input  FM_CPU0_SLPS3_FPGA_R_LVC18_N,
    input  FM_CPU1_SLPS4_LVC18_N,
    inout  FM_CPU0_ADR_TRIGGER_LVC18_N,
    input  FM_CPU1_GLB_RST_WARN_LVC18_N,
    input  FM_CPU1_REFCLK_RDY_R_FPGA_LVC18,
    inout  ESPI_CPU0_IO0_FPGA_R_LVC18,
    output FM_CPU0_PWRBTN_FPGA_R_LVC18_N,
    output IRQ_ESPI_CPU0_ALERT1_FPGA_LVC18_N,

    input  RST_CPU0_PLTRST_SYNC_FPGA_LVC18_R_N,
    
    input  ESPI_CPU0_CS1_FPGA_R2_LVC18_N,
    
    input  FM_CPU0_GLB_RST_WARN_FPGA_LVC18_N_R,
    input  FM_GLBRST_HALT_MODE_RP,
    input  RST_ESPI_CPU0_FPGA_R_LVC18_N,
    output UART_CPU1_CTS_LVC18_R3,
    output IRQ_ESPI_CPU0_ALERT0_FPGA_LVC18_N,
    input  UART_CPU1_RTS_LVC18_R3,
    input  ESPI_CPU0_CS0_FPGA_R2_LVC18_N,
    input  FM_CPU0_REFCLK_RDY_R_FPGA_LVC18_OD,
    input  FM_CPU1_RIGHT_RISER_MODE_LVC18_N,
    output IRQ_CPU1_WAKE_LVC18_R_N,
    inout  ESPI_CPU1_IO1_FPGA_R_LVC18,
    inout  ESPI_CPU1_IO3_FPGA_R_LVC18,
    inout  ESPI_CPU1_IO2_FPGA_R_LVC18,
    input  FM_CPU0_TPM_CONN_PRSNT_COD18_N,
    output UART_CPU1_RXD_LVC18_R3,
    input  CLK_66M_ESPI_CPU0_FPGA_R_LVC18,
    input  FM_CPU0_LEFT_RISER_MODE_LVC18_N,
    input  SGPIO_MAIN_MOD_FPGA_LD_LVC18_N,
    input  FM_CPU0_LEFT_RISER_WIDTH_LVC18,
    input  CLK_66M_ESPI_CPU1_FPGA_R_LVC18,
    input  FM_HPM_STBY_RST_LVC18_N,
    input  SGPIO_MAIN_MOD_FPGA_DOUT_LVC18,
    output RST_PLTRST_CPU0_PLD_LVC18_N,
    output RST_PLTRST_CPU1_PLD_R_LVC1_N,
    output FM_P1V0_AUX_LVC18_EN,
    output RST_BMC_PCIE_MUX_R_LVC18_N,

    output FM_PVCCIN_CPU1_R_LVC18_EN,

    input  FM_FORCE_PWRON_LVC18,

    output FM_P1V1_AUX_LVC18_EN,

    output RST_PLTRST_CPU0_TPM_PLD_LVC18_N,

    output FM_DBG_MUX_TDO_CTRL,
    output DBP_PMODE_R_LVC18,

    output RST_PLTRST_CPU1_TPM_PLD_LVC18_N,

    input  FM_CPU1_RIGHT_RISER_WIDTH_LVC18,

    output RST_BMC_HSBP_MUX_LVC18_N,

    input  FM_PCIE_FV_BIF_EN,

    output FM_SYS_THROTTLE_R_LVC3_N,
    input  SGPIO_MAIN_MOD_FPGA_CLK_LVC18,
    output FM_HPM_STBY_RDY_LVC18,
    input  FM_HPM_STBY_EN_LVC18,
    output RST_CPU0_PE1_EDSFFX4_PERST0_PLD_R_N,
	
	output SPEAKER_BMC_R

 );

   //-------------------------------------------------------------
   //Parameters definitions

   localparam LVDS_REGS = 66;                       //for LVDS glitchfiltering/synch
   wire   Reset;
   //IntrPrstn & type

   wire                         wCpu0IntrPrsnt_n;
   wire                         wCpu1IntrPrsnt_n;
   wire                         wCpu0IntrTypeABn;
   wire                         wCpu1IntrTypeABn;

   //-------------------------------------------------------------
   //Registers Declarations

   //SMBus update
   reg                          i2c_pfr_data_in; 
   reg                          i2c_pfr_clk_in; 
   reg                          i2c_pfr_data_sync; 
   reg                          i2c_pfr_clk_sync;

   
   //-------------------------------------------------------------
   //Wires Declarations

   wire [5:0]                   wBoardId;
   wire                         wInModular;
   wire                         wInRP;
   
   wire                         wIBL_RDY_N;
   wire                         wH_CPU0_MEMHOT_IN_LVC1_R_N;
   wire                         wH_CPU1_MEMHOT_IN_LVC1_R_N;
   wire                         wH_CPU0_PROCHOT_LVC1_R_N;
   wire                         wH_CPU1_PROCHOT_LVC1_R_N;

   //from internal PLL

   wire                         wClk_2M, wClk_20M, wClk_100M, wClk_25M, wClk_50M;
   wire                         wDRst_n, wRst_n;                                      //from PLL lock output
   
   wire                         wClk_2M_adc, wClk_25M_adc;
   wire                         wAdcPllLocked;
   
   //from ESPI
   wire                         wFM_ADR_MODE0;

   wire [3:0]                   pwr_err_source;
   wire                         pwr_restart;
   wire                         pwr_restart_clear;
   wire                         force_to_enter_err_clear;
   wire                         force_to_enter_err;

    //ADR
    wire        iFM_CPU0_ADR_TRIGGER_N;   //ADR Triggerred by CPU
    wire        oFM_CPU0_ADR_TRIGGER_N;   //ADR Triggerred by FPGA
    wire [31:0] ADRcounter1;
    wire [31:0] ADRcounter2;

   wire [1:0]                   uart_rxd;
   wire [1:0]                   uart_cts;
   wire [1:0]                   uart_txd;
   wire [1:0]                   uart_rts;

   //To Secondary FPGA via sGPIO
   wire [3:0]                   wMASTER_POST_CODE;
   wire [7:0]                   wCPU0_FLT_CODE;                     
   wire [7:0]                   wCPU1_FLT_CODE;
   wire [5:0]                   wCPU0_DIMM_FLT_CODE;
   wire [5:0]                   wCPU1_DIMM_FLT_CODE;
   
   wire [2:0]                   wPSU_FLT_CODE;
   wire                         w_OcpPwrFlt_LED;
   
   wire                         wPldHeartBeat;

   wire                         wFM_PERST_TIMING_SEL;               //from board to Secondary, then to Main thru SGPIO
   wire                         wFmCpu1SktOccBypass;                //if Cpu1SktOcc is bypassed or not
   wire                         wSMPldUpgradeAck;                   //received from Secondary/Modular and fwd thru LVDS to SCM
   wire                         wSMPldUpgradeSync;                  //received from SCM thru LVDS and fwd to Secondary/Modular
   wire                         wRST_PLTRST_CPU0_PLD_LVC18_N;
   wire                         wFM_BMC_ONCTL_ACK_N;                //BMC ONCTL Acknowledge
   wire                         wFM_BMC_ONCTL_LVDS_N;
   wire                         wHPfrEna;                           //Hierarchical PFR Enable
   wire                         wLegacyNode;                        //asserted it we are in legacy node
   wire                         wPfrGlobalAck;                      //PFR Global Acknowledge (to be passed thru LVDS)
   wire                         wModularPrsnt;                       //We are in modular board
   wire                         wSMRJODone;                         //Secondary-Modular Remote Jumper Override Routine is Done

   reg                          wCpu0BiosPostCmplt_n;
   reg                          wCpu1BiosPostCmplt_n;

   wire                         wH_CPU0_THERMTRIP_LVC1_N;
   wire                         wH_CPU1_THERMTRIP_LVC1_N;

   wire                         wH_CPU0_MEMTRIP_LVC1_N;
   wire                         wH_CPU1_MEMTRIP_LVC1_N;

   wire [(LVDS_REGS*8)-1:0]     wMain2ModPData;
   wire                         wMain2ModStartBit;
   wire                         wFmCpu0IntrpsrCablePrsnt;
   wire                         wFmCpu1IntrpsrCablePrsnt;
   wire                         wVAL_DBG_JUMPER_EN_N;
   wire                         wS5With12V_n;
   wire                         wMCpu1PartitionId0;
   wire                         wMCpu0PartitionId0;
   
   wire                         wHpmStbyRst_n;
   
   wire [129:0]                 wMain2ModSpare;

   wire                         wPWRGD_PVNN_MAIN_CPU0_FF;
   wire                         wPWRGD_PVNN_MAIN_CPU1_FF;
   
   
   //lvds

   wire                         wCPU_MISMATCH;
   wire                         wMEM_PWR_FLT;
   wire                         wCPU_PWR_FLT;
   wire                         wPSU_FAULT;

   wire                         wP3V3_FAULT;
   wire                         wCPU_AUX_PWR_FLT;
   wire                         wFM_DUAL_PARTITION_R_N;
   wire                         wFM_BIOS_IMAGE_SWAP_N;
   wire                         wRST_PLTRST_SYNC_CPU0_PLD_N;

   wire                         wRST_PLTRST_SYNC_CPU1_PLD_N;
   wire                         wFM_BMC_SAFS_SEL;
   wire                         wPWRGD_PS_PWROK_CPU_PLD_R;
   wire                         wFM_SLPS4_CPU0_CPU_PLD_N;
   wire                         wFM_SLPS3_CPU0_CPU_PLD_N;
   wire                         wPWRGD_CPU0_LVC1_R;
   wire                         wFM_SLPS4_CPU1_CPU_PLD_N;
   wire                         wFM_SLPS3_CPU1_CPU_PLD_N;
   
   //synch/gfilter for lvds
   wire                         wRstCpu0PltrstSync_FF;
   wire                         wRstCpu1PltrstSync_FF;
   wire                         wIrqSml1PmbusPldAlert_n_FF;
   wire                         wCpu0ThermtripFpga_n_FF;
   wire                         wCpu1ThermtripFpga_n_FF;
   wire                         wCpu0MemtripFpga_n_FF;
   wire                         wCpu1MemtripFpga_n_FF;
   wire                         wCpu0MemhotOutFpga_n_FF;
   wire                         wCpu1MemhotOutFpga_n_FF;
   wire                         wCpu0Caterr_n_FF;
   wire                         wCpu0Rmca_n_FF;
   wire                         wCpu1Caterr_n_FF;                 
   wire                         wCpu1Rmca_n_FF;
   wire                         wCpu0Err0Fpga_n_FF;
   wire                         wCpu0Err1Fpga_n_FF;
   wire                         wCpu0Err2Fpga_n_FF;
   wire                         wCpu1Err0Fpga_n_FF;
   wire                         wCpu1Err1Fpga_n_FF;
   wire                         wCpu1Err2Fpga_n_FF;
   wire                         wCpu0MonFail_n_FF;
   wire                         wCpu1MonFail_n_FF;
   wire                         wFpPwrBtn_n_FF;
   wire                         wFpRstBtn_n_FF;
   wire                         wFpIdBtn_n_FF;
   wire                         wFpNmiBtn_n_FF;
   wire                         wFmSmbBmcNvmeAlert_n_FF;
   wire                         wIrqSml1PmbusAlert_n_FF;
   wire                         wIrqCpu0VrHot_n_FF;
   wire                         wIrqCpu1VrHot_n_FF;
   wire                         wIrqCpu0MemVrHot_n_FF;
   wire                         wIrqCpu1MemVrHot_n_FF;
   wire                         wS3MCpu0CpldCrcError_FF;
   wire                         wS3MCpu1CpldCrcError_FF;
   wire                         wDbpPodPrsnt_n_FF;
   wire                         wASDEnDet;
   wire                         wCpu0Thermtrip_n_FF;
   wire                         wCpu0Memtrip_n_FF;
   wire                         wCpu0MemHotOut_n_FF;
   wire                         wCpu0Err0_n_FF;
   wire                         wCpu0Err1_n_FF;
   wire                         wCpu0Err2_n_FF;
   wire                         wCpu1Thermtrip_n_FF;
   wire                         wCpu1Memtrip_n_FF;
   wire                         wCpu1MemHotOut_n_FF;
   wire                         wCpu1Err0_n_FF;
   wire                         wCpu1Err1_n_FF;
   wire                         wCpu1Err2_n_FF;
   
   
   
   wire                         wRstBmcSrstDio_n;
   
   wire [1:0]                   wCpu0CatErrEncode;  //CPU0 CATERR encoded to send to BMC thru BMC
   wire [1:0]                   wCpu1CatErrEncode;  //CPU1 CATERR encoded to send to BMC thru BMC
   wire [1:0]                   wCpu0RmcaEncode;    //CPU0 RMCA encoded to send to BMC thru BMC
   wire [1:0]                   wCpu1RmcaEncode;    //CPU1 RMCA encoded to send to BMC thru BMC
   
   
   
   
   //pfr i2c_slave avmm intf
   wire [15: 0]                 avmm_pfr_address;   
   wire [15: 0]                 avmm_pfr_writedata; 
   wire                         avmm_pfr_write;     
   wire                         avmm_pfr_read; 
   wire                         avmm_pfr_readvalid;
   wire [15: 0]                 avmm_pfr_readdata; 
   wire [15: 0]                 avmm_pfr_readdata_h;

   //i2c_slave for PFR   
   wire                         i2c_pfr_data_oe; 

   //avmm connected between i2c & rsu
   wire [31: 0]                 avmm_rsu_address;      
   wire                         avmm_rsu_write;        
   wire [31: 0]                 avmm_rsu_writedata;    
   wire                         avmm_rsu_read;         
   wire [31: 0]                 avmm_rsu_readdata;     
   wire                         avmm_rsu_readdatavalid;
   
   //avmm connected to scm pfr csr
   wire [31: 0]                 main_pfr_csr_address;      
   wire                         main_pfr_csr_write;        
   wire [31: 0]                 main_pfr_csr_writedata;    
   wire                         main_pfr_csr_read;         
   wire [31: 0]                 main_pfr_csr_readdata;     
   wire                         main_pfr_csr_readdatavalid;
   wire                         main_pfr_csr_waitrequest;  
   wire [ 3: 0]                 main_pfr_csr_byteenable;
   
 

   //Connect to CPU side MCSI internal CSR
   wire [31:0]                  mcsi_csr_address;       
   wire                         mcsi_csr_write;         
   wire [31:0]                  mcsi_csr_writedata;     
   wire                         mcsi_csr_read;          
   wire [31:0]                  mcsi_csr_readdata;      
   wire                         mcsi_csr_readdatavalid; 
   wire                         mcsi_csr_waitrequest;   
   wire [ 3:0]                  mcsi_csr_byteenable;
   
   //Connect to ADC module
   wire [31:0]                  adc_csr_address;       
   wire                         adc_csr_write;         
   wire [31:0]                  adc_csr_writedata;     
   wire                         adc_csr_read;          
   wire [31:0]                  adc_csr_readdata;      
   wire                         adc_csr_readdatavalid; 
   wire                         adc_csr_waitrequest;   
   wire [3:0]                   adc_csr_byteenable;

   //AVMM Master interface tunneling through LVDS
   wire [15:0]                  avmm_mst_addr;  
   wire                         avmm_mst_read;  
   wire                         avmm_mst_write;
   wire [31:0]                  avmm_mst_wdata;
   wire [3:0]                   avmm_mst_byteen;
   wire [31:0]                  avmm_mst_rdata;
   wire                         avmm_mst_rdvalid;
   wire                         avmm_mst_waitrq;
   
   //Connect to CPU side local CSR
   wire [31:0]                  main_csr_address;       
   wire                         main_csr_write;         
   wire [31:0]                  main_csr_writedata;     
   wire                         main_csr_read;          
   wire [31:0]                  main_csr_readdata;      
   wire                         main_csr_readdatavalid; 
   wire                         main_csr_waitrequest;   
   wire [3:0]                   main_csr_byteenable;

   //Connect to I2C_Master which interconnects with Debug CPLD
   wire [31:0]                  wSecondaryAddress;       
   wire                         wSecondaryWrite;         
   wire [31:0]                  wSecondaryWriteData;
   wire                         wSecondaryRead;
   wire [31:0]                  wSecondaryReadData;
   wire                         wSecondaryReadDataValid;
   wire                         wSecondaryWaitReq;
   wire [3:0]                   wSecondaryByteEna;
   
   //i2c master to debug cpld
   wire                         wI2CSecondaryDataIn; 
   wire                         wI2CSecondaryClkIn;  
   wire                         wI2CSecondaryDataOe; 
   wire                         wI2CSecondaryClkOe;

   //IOC LVDS ports
   wire                         wTxCoreClk;
   wire                         wTxPllLock;
   wire [13:0]                  wSclRsvd;
   wire [13:0]                  wSdaRsvd;
   wire [119:0]                 wLvdsGpioIn;
   wire [119:0]                 wLvdsGpioOut;

   wire                         wMcsiAligned;

   wire                         wUPI_INIT_DONE;

   //LVDS from SCM to Main PLD
   wire                         wCpu1IntrClkConfDone;
   wire                         wCPLD_RSU_HIDE;
   wire                         wCPLD_RSU_HIDE_sync;
   wire [7:0]                   wSCMFPGAREV;
   wire [7:0]                   wSCMFPGATEST;
   wire                         FM_TTK_SPI_EN_RJC_N_IN;
   wire                         PFR_DEBUG_JUMPER_RJC_N_IN;
   wire                         PFR_FORCE_RECOVERY_RJC_N_IN;
   wire                         wFM_BMC_INIT_DONE;
   wire                         wFM_GLOBAL_RESET;
   wire [7:0]                   wLED_CPU0_DIMM_CH1_8_FLT;        //CPU0 DIMMs FAULT CODE (CHs 1-8) for LEDs on Secondary PLD (thru SGPIO)
   wire [7:0]                   wLED_CPU1_DIMM_CH1_8_FLT;        //CPU1 DIMMs FAULT CODE (CHs 1-8) for LEDs on Secondary PLD (thru SGPIO)
   wire                         wSURPRISE_RESET;
   wire                         RST_BMC_HSBP_MUX_R_N;
   wire                         wFM_BMC_ONCTL_N;
   wire                         wFM_BMC_BMCINIT;
   wire                         wFM_SKT0_FAULT_LED;
   wire                         wFM_SKT1_FAULT_LED;
   wire                         wPfrLocalSync;
   wire                         wFM_TPM_EN_PULSE;

   wire                         wSCM_BMC_AUX_PWR_OK;     
   wire                         wSCM_BMC_AUX_PWR_FAULT;  
   wire                         wSCM_PWR_FAULT;          
   wire                         wBMC_PWR_FAULT;          
   wire                         wP5V_MAIN_PWR_FAULT;     
   wire                         wAUX_PWRGD_CPU0_SCM;     
   wire                         wAUX_PWRGD_CPU1_SCM;
   wire                         wFM_CK440Q_SSC0_R_LVC3;
   wire                         wFM_CK440Q_SSC1_R_LVC3;

   wire                         wBIOS_POST_CODE_LED_0;   
   wire                         wBIOS_POST_CODE_LED_1;   
   wire                         wBIOS_POST_CODE_LED_2;   
   wire                         wBIOS_POST_CODE_LED_3;   
   wire                         wBIOS_POST_CODE_LED_4;   
   wire                         wBIOS_POST_CODE_LED_5;   
   wire                         wBIOS_POST_CODE_LED_6;   
   wire                         wBIOS_POST_CODE_LED_7;   
   wire                         wPFR_POST_CODE_LED_0;    
   wire                         wPFR_POST_CODE_LED_1;    
   wire                         wPFR_POST_CODE_LED_2;    
   wire                         wPFR_POST_CODE_LED_3;    
   wire                         wPFR_POST_CODE_LED_4;    
   wire                         wPFR_POST_CODE_LED_5;    
   wire                         wPFR_POST_CODE_LED_6;    
   wire                         wPFR_POST_CODE_LED_7;

   wire                         wCPU1_AUX_PWR_OK;
   wire                         wCPU0_AUX_PWR_OK;
   //---------------------------------------------------------------------------------
   //sgpio from Main2Mod

   wire [7:0]                   wLED_STATUS;
   wire                         wSCM_BMC_EN;


   //-------------------------------------------------------------
   //for OD outputs

   wire                         wFM_I3CHUB_DBG_MSEL;
   wire                         wFM_SYS_THROTTLE_R_N;
   wire                         wRST_BMC_HSBP_MUX_N;
   wire                         wRST_BMC_PCIE_MUX_R_N;
   wire                         wRST_CPU0_RTCRST_N;
   wire                         wRST_CPU1_RTCRST_N;
   
   
   //-------------------------------------------------------------
   
   //modular
   wire                         wFM_STANDALONE_MODE_N;
   wire                         wFM_4S_8S_MODE_N;
   wire                         wFM_NODE_ID0;
   wire                         wFM_NODE_ID1;
   
   //-------------------------------------------------------------

   //other
   wire                         wFM_SMB_BMC_NVME_LVC3_ALERT_N;
   wire                         PUD_TS3DS10224_SAI_R;
   wire                         Reset_N;

   wire                         wCPU_AUX_PWRGD_Partition_Sel;
   //-------------------------------------------------------------
   
   wire                         wFM_DUAL_PARTITION_LVC3_N;
   wire                         wFM_PARTITION_SEL_LVC3;
   
   //wires for debug 
   wire                         wRtcRstOvrrdCpu0Sel, wRtcRstOvrrdValCpu0, wRtcRstOvrrdCpu1Sel, wRtcRstOvrrdValCpu1;
   

   //IIC_MM error handling
   wire                         invalid_access_adc;
   wire                         invalid_access_cpu_glb;
   wire                         invalid_access_cpu_mcsi;
   wire                         invalid_access_cpu;
   wire                         invalid_access_dbg;

   //Instances

   //------------------------------------------------------------------------------------------------------
   //ESPI

   wire                         espi0_avmm_write;    
   wire                         espi0_avmm_read;     
   wire [31:0]                  espi0_avmm_writedata;
   wire [ 4:0]                  espi0_avmm_address;  
   wire [31:0]                  espi0_avmm_readdata;

   
   //eSPI slave connected to CPU0_CS1 for vGPIO Expansion.
   localparam DEVICE_FAMILY              = "MAX 10 FPGA";
   localparam IO_MODE_RANGE              = 2'b11;
   localparam OPEN_DRAIN_ALERT_EN        = 1'b0;
   localparam MAX_FREQ_RANGE             = 3'b000;
   localparam CHANNEL_SUPPORT            = 8'b00000011;
   localparam MAX_PC_PAYLOAD_SIZE_RANGE  = 3'b001;
   localparam MAX_PC_READREQ_SIZE_RANGE  = 3'b001;
   localparam MAX_OOB_PAYLOAD_SIZE_RANGE = 3'b001;
   localparam MAX_VW_COUNT_SUPPORTED     = 6'b000111;

   localparam TABLE_VERSION              = 32'h0000_0000;

   wire [3:0]                   espi_data_in;
   wire [3:0]                   espi_data_out;
   wire [31:0]                  table_version;
   wire [7:0]                   plt_csr4;
   wire [7:0]                   plt_csr5;
   wire [7:0]                   plt_csr6;
   wire [7:0]                   plt_csr7;
   wire [7:0]                   plt_csr8;
   wire [7:0]                   plt_csr9;
   wire [7:0]                   plt_csra;
   wire [7:0]                   plt_csrb;
   wire [7:0]                   plt_csrc;
   wire [7:0]                   plt_csrd;
   wire [7:0]                   plt_csre;
   wire [7:0]                   plt_csrf;
   wire [31:0]                  device_id_reg;
   wire [31:0]                  general_config_reg;
   wire [31:0]                  channel0_config_reg;
   wire [31:0]                  channel1_config_reg;
   wire [31:0]                  channel2_config_reg;
   wire [31:0]                  channel3_config_reg;

   

   //I2C AVMM
   wire [31:0]  secondary_csr_address;
   wire         secondary_csr_write;
   wire [31:0]  secondary_csr_writedata;
   wire         secondary_csr_read;
   wire [31:0]  secondary_csr_readdata;
   wire         secondary_csr_readdatavalid;
   wire         secondary_csr_waitrequest;
   wire [ 3:0]  secondary_csr_byteenable;
   
  //AVMM Master 2 interface of i2c Host
   wire [31:0]                  avmm_host_mst_addr;
   wire                         avmm_host_mst_read;
   wire                         avmm_host_mst_write;
   wire [31:0]                  avmm_host_mst_wdata;
   wire [3:0]                   avmm_host_mst_byteen;
   wire [31:0]                  avmm_host_mst_rdata;
   wire                         avmm_host_mst_rdvalid;
   wire                         avmm_host_mst_waitrq;
   
   //Connect to I2C_Master which interconnects with Debug CPLD
   wire [31:0]  secondary_address;
   wire         secondary_write;
   wire [31:0]  secondary_writedata;
   wire         secondary_read;
   wire [31:0]  secondary_readdata;
   wire         secondary_readdatavalid;
   wire         secondary_waitrequest;
   wire [ 3:0]  secondary_byteenable;
   
   //Wires for connect to mux 5 slaves with rjo module
   wire [31:0]  rjo_address        ;
   wire         rjo_write          ;
   wire [31:0]  rjo_writedata      ;
   wire         rjo_read           ;
   wire [31:0]  rjo_readdata       ;
   wire         rjo_readdatavalid  ;
   wire         rjo_waitrequest    ;
   wire [ 3:0]  rjo_byteenable     ;
   
   wire wGLBRST_HOLD_OFF_EN;
   wire wGLBRST_HOLD_OFF;
   wire FM_CPU0_GLB_RST_WARN_PLD_N_FF;
   wire wGLBRST_STATUS;
   wire wFM_SKT0_FAULT_LED_SECFPGA;
   wire wFM_GLBRST_HALT_MODE;
   wire wFM_GLBRST_HALT_MODE_MOD;
   
   wire wH_CPU1_MEMTRIP_LVC1_R2_N;                                                   
   wire wIRQ_ESPI_CPU0_ALERT1_FPGA_LVC18_N;
   wire wFM_RST_PERST_BIT3_LVC25, FM_DUAL_PARTITION_HDR_LVC25_N;
   wire RST_PLD_PCIE_CPU0_x16_PERST_LVC3_R_N, RST_PLD_PCIE_CPU0_DCSCM_PERST_LVC3_R_N;
   wire [2:0] wFM_BOARD_REV_ID;
   wire wFM_DUAL_PARTITION_QS_LVC3_N;

 wire rjo_ready;
 wire flag_source;

 //flash avmm intf--RJU
   wire          RSU_flash_csr_addr;
   wire          RSU_flash_csr_read;
   wire [31: 0]  RSU_flash_csr_writedata;
   wire          RSU_flash_csr_write;
   wire [31: 0]  RSU_flash_csr_readdata;
   wire [31: 0]  RSU_flash_data_addr;
   wire          RSU_flash_data_read;
   wire [31: 0]  RSU_flash_data_writedata;
   wire          RSU_flash_data_write;
   wire [31: 0]  RSU_flash_data_readdata;
   wire          RSU_flash_data_waitrequest;
   wire          RSU_flash_data_readdatavalid;
   wire [ 6: 0]  RSU_flash_data_burstcount;

   wire I2C_CRC_Error;

   wire wIRQ_BMC_CPU_NMI_P0;
   wire wNMI_SEL_CPU_eSPI;
   wire wCPU_IRQ_NMI_ESPI;

   //wires for CSR power sequence
   wire [31:0] wstatus_pwr_seq_1;
   wire [31:0] wstatus_pwr_seq_2;
   wire [31:0] wstatus_pwr_seq_3;
   wire [31:0] wstatus_pwr_seq_4;
   wire [31:0] wsel_mux_dbg;

   // wires for Sync HPM_STBY_RDY
   wire wFM_HPM_STBY_RDY_ACK;
   wire wFM_HPM_STBY_RDY_LVC18;


   // PLTRST synchronizer
   reg              rIblRdyMeta_n;
   reg              rIblRdySync2M_n;
   reg              rRstPltRstPfrMeta_n;
   reg              rRstPltRstPfrSync2M_n;
   reg              rRstPltRstPfrMeta2_n;
   reg              rRstPltRstPfrSyncSGPIO_n;

   
   // regs for synchronizers in SGPIO
   reg rFmHpmStbyRdy_SyncSGPIO,              rFmHpmStbyRdy_r1SyncSGPIO;
   reg rRstPltrstCpu1PldR_n_SyncSGPIO,       rRstPltrstCpu1PldR_n_r1SyncSGPIO;
   reg rFmAsdEnDet_SyncSGPIO,                rFmAsdEnDet_r1SyncSGPIO;
   reg rPwrgdPvnnMainCpu1_SyncSGPIO,         rPwrgdPvnnMainCpu1_r1SyncSGPIO;
   reg rPwrgdPvnnMainCpu0_SyncSGPIO,         rPwrgdPvnnMainCpu0_r1SyncSGPIO;
   reg rPwrgdCpu1Fpga_SyncSGPIO,             rPwrgdCpu1Fpga_r1SyncSGPIO;
   reg rPwrgdCpu0S0PwrokR_SyncSGPIO,         rPwrgdCpu0S0PwrokR_r1SyncSGPIO;
   
   reg rFmThermtripCpu0LedLatched_SyncSGPIO, rFmThermtripCpu0LedLatched_r1SyncSGPIO;
   reg rFmThermtripCpu1LedLatched_SyncSGPIO, rFmThermtripCpu1LedLatched_r1SyncSGPIO;
   
   reg rHCpu1CaterrR2_n_SyncSGPIO,           rHCpu1CaterrR2_n_r1SyncSGPIO;
   reg rHCpu0CaterrR2_n_SyncSGPIO,           rHCpu0CaterrR2_n_r1SyncSGPIO;
   reg rFmPartitionSel_SyncSGPIO,            rFmPartitionSel_r1SyncSGPIO;
   reg rFmDualParition_SyncSGPIO,            rFmDualParition_r1SyncSGPIO;
   
   reg rPwrgdCpu0PltAuxPwrgdFpga_SyncSGPIO,  rPwrgdCpu0PltAuxPwrgdFpga_r1SyncSGPIO;
   reg rRstCpu0_n_SyncSGPIO,                 rRstCpu0_n_r1SyncSGPIO;
   
   reg rFmDualPartitionQs_n_SyncSGPIO,       rFmDualPartitionQs_n_r1SyncSGPIO;
   
   reg rMbvrReadySync_SyncSGPIO,             rMbvrReadySync_r1SyncSGPIO;
   
   ////////////////////////////////////////////////////////////
   // wires for synchronizers in espi
   
   wire wCpuIrqNmiEspi_SyncESPI;
   wire wPwrgdCpu0PltAuxPwrgdFpga_SyncESPI;
   wire wCpu0IntrPrsnt_n_SyncESPI;
   wire wCpu1IntrPrsnt_n_SyncESPI;
   wire wCpu0IntrTypeABn_SyncESPI;
   wire wCpu1IntrTypeABn_SyncESPI;
   wire wFmPcieFvBifEn_SyncESPI;
   wire wFM_PCIE_FV_BIF_EN;
   
   //// wires and regs for rjo

   localparam JUMPER_COUNT    = 6'd48;// define number of physical jumper

   wire [JUMPER_COUNT-1:0] wOverrideValue  ;  // wire ovelue overrided
   reg [JUMPER_COUNT-1:0]  rCurrentValue   ;  // value overrided or value direct of pin
   wire [JUMPER_COUNT-1:0] Jumper          ;  // wire of physical pin
   wire [JUMPER_COUNT-1:0] wOvEnable_n     ;  //override is enable in level low

   wire   wRST_CPU0_RTCRST_PLD_R_N;
   wire   wRST_CPU0_RTCRST_PLD_R_N_RJO;
   wire   wFM_BMCINIT_DISABLE_LVC25_N;
   wire   wFM_CPU0_PKGID0;
   wire   wFM_CPU0_PKGID1;
   wire   wFM_CPU0_PKGID2;
   wire   wFM_CPU1_PKGID0;
   wire   wFM_CPU1_PKGID1;
   wire   wFM_CPU1_PKGID2;
   wire   wPFR_DEBUG_JUMPER_RJC_N_IN;
   wire   wPFR_FORCE_RECOVERY_RJC_N_IN;
   wire   wFM_TTK_SPI_EN_RJC_N_IN;
   wire   wFM_RST_PERST_BIT0_LVC25;
   wire   wFM_RST_PERST_BIT1_LVC25;
   wire   wPWRGD_CPU0_PLT_AUX_PWRGD_FPGA_LVC18_R;
   wire   wFM_PASSWORD_CLEAR_LVC25_N;
   wire   wFM_ASD_EN_DET_LVC3;
   wire   wFM_CPU0_SKTOCC_LVT3_PLD_N;
   wire   wFM_CPU1_SKTOCC_LVT3_PLD_N;
   wire   wFM_PS_EN_PLD_R_LVC3;
   wire   wFM_SERIAL_BOOT;
   wire   wFM_CPU0_ADR_EXT_TRIGGER_LVC25_N;
   wire   wFM_CPU1_ADR_EXT_TRIGGER_LVC25_N;
   wire   wH_CPU0_THERMTRIP_FPGA_LVC1_R_N;
   wire   wH_CPU1_THERMTRIP_LVC1_R2_N;
   wire   wRST_PLTRST_CPU0_TPM_PLD_LVC18_N;

   // wires for synchronizers in LVDS

   wire   wFmCpu0sktoccPld_nSyncLvds;
   wire   wFmCpu1sktoccPld_nSyncLvds;
   wire   wMcsiAlignedSync2M;
   wire   wCpu1IntrClkConfDoneSync2M;
   wire   wAuxPwrGdCpu0ScmSync2M;
   wire   wAuxPwrGdCpu1ScmSync2M;
   wire   wFmCpu0IntrpsrCablePrsntSync2M;
   wire   wFmCpu1IntrpsrCablePrsntSync2M;
   wire   wBmcOnctlSync2M;
   wire   wScmBmcAuxPwrOKSync2M;
   wire   wScmBmcAuxPwrFaultSync2M;
   wire   wSurpriseResetSync2M;
   wire   wGlobalResetSync2M;
   wire   wPwrGdP1V0AuxSync2M;
   wire   wPwrGdP1V1AuxSync2M;
   wire   wRstCpu0PltrstSyncFpgaSync2M_n;
   wire   wRstPltrstCpu1PldSync2M_n;
   wire   wForceToEnterErrSync2M;
   wire   wLegacyNodeSync2M;
   wire   wGlbRstHoldOffEnaSync2M;
   wire   wGlbRstHoldOffSync2M;
   wire   wGlbRstHaltModeSync2M;
   wire   wPwrGdP1V2Max10AuxSync2M;
   wire   wRjoReadySync2M;
   wire   wRjoReadySecSync2M;
   
   wire   wFM_CPU0_PWRBTN_FPGA_R_LVC18_N;
   wire   wRST_CPU0_RSTBTN_FPGA_LVC18_R_N;
   wire   wFmCpu0PwrbtnFpgaSync2M_n;
   wire   wFmRstCpu0RstBtnFpgaSync2M_n;


   wire        wCpu1AuxPwrOkSyncLvds;
   wire        wCpu1ThermtripSyncLvds_n;
   wire        wCpu0MemtripSyncLvds_n;
   wire        wCpu0ThermtripSyncLvds_n;
   wire [1:0]  wCpu1RmcaEncodeSyncLvds;
   wire [1:0]  wCpu1CatErrEncodeSyncLvds;
   wire [1:0]  wCpu0RmcaEncodeSyncLvds;
   wire [1:0]  wCpu0CatErrEncodeSyncLvds;
   wire        w1200VaOCSyncLvds;
   wire        wSlpS3Cpu1SyncLvds_n;
   wire        wSlpS4Cpu1SyncLvds_n;
   wire        wPwrGdCpu0SyncLvds;
   wire        wSlpS3Cpu0SyncLvds_n;
   wire        wSlpS4Cpu0SyncLvds_n;
   wire        wCpu0Gpio4EafBmcSafsSelSyncLvds;
   wire        wBiosImageSwapSyncLvds_n;
   wire        wValDbgJumperEnSyncLvds_n;
   wire        wCpuAuxPwrFltSyncLvds;
   wire        wP3V3FaultSyncLvds;
   wire        wPsuFaultSyncLvds;
   wire        wCpuPwrFltSyncLvds;
   wire        wMemPwrFltSyncLvds;
   wire        wCpuMismatchSyncLvds;
   wire        wPwrGdCpu0S0PwrOkSyncLvds;
   wire        wPwrgdCpu0PltAuxPwrgdFpga_RJOSync;
   wire        wRstPltrstCpu0TpmPld_n_RJOSync;
   wire        wPwrgdPvnnMainCpu0_SyncLvds;

   wire        wFM_HPFR_OUT, wFmHpfrOut_sync2M;
   wire        wFmHpfrInSyncLvds;
   wire        wFmLegacySyncLvds;
   wire        wFmHpfrActive;
   wire        wPfrGlobalAck_toLVDS;
   wire        wLegacyNode_toLVDS;  
   
   wire        wMBVR_ready_sync;  // MBVR flow in Modular
   wire        wMBVR_ready_ack;   // MBVR flow in Modular
   wire        wMbvrReadyAckSync2M;
   
   wire        oFM_THERMTRIP_CPU0_LED_LATCHED;
   wire        oFM_THERMTRIP_CPU1_LED_LATCHED;
   
   wire        wFmTtkSpiEnRjc_nSyncLvds;
   wire        wFmPfrDebugJumperRjc_nSyncLvds;
   wire        wPfrForceRecoveryRjc_nSynLvds;
   
   // MBVR Flow for Modular
   wire wRST_PLD_PCIE_CPU0_x16_PERST_LVC3_R_N;
   wire wRST_PLD_PCIE_CPU0_DCSCM_PERST_LVC3_R_N;
   wire wRST_PLD_PCIE_CPU0_DEV_PERST_LVC3_R_N;
   wire wRST_PLD_PCIE_CPU1_DEV_PERST_LVC3_R_N;
   wire wDoneTimer_20ns_CPU0;
   wire wDoneTimer_20ns_CPU1;
   wire wDoneTimer_20ns_DCSCM;
   

   localparam T_20ns_100M = 4'd2;

   
   
   ///////////////////////////
   ////// L O G I C  /////////

assign wH_CPU1_MEMTRIP_LVC1_R2_N = wInModular ? 1'b1 : H_CPU1_MEMTRIP_LVC1_R2_N;

// Tri-state buffer for eSPI IO
  
   assign {ESPI_CPU0_IO3_FPGA_R_LVC18, ESPI_CPU0_IO2_FPGA_R_LVC18, ESPI_CPU0_IO1_FPGA_R_LVC18, ESPI_CPU0_IO0_FPGA_R_LVC18} = (RST_ESPI_CPU0_FPGA_R_LVC18_N && !ESPI_CPU0_CS1_FPGA_R2_LVC18_N) ? espi_data_out : 4'bzzzz;
   assign espi_data_in = {ESPI_CPU0_IO3_FPGA_R_LVC18, ESPI_CPU0_IO2_FPGA_R_LVC18, ESPI_CPU0_IO1_FPGA_R_LVC18, ESPI_CPU0_IO0_FPGA_R_LVC18};


   vgpio_espi_wrapper
     #(
       .DEVICE_FAMILY                   ( DEVICE_FAMILY                     ),
       .IO_MODE_RANGE                   ( IO_MODE_RANGE                     ),
       .OPEN_DRAIN_ALERT_EN             ( OPEN_DRAIN_ALERT_EN               ),
       .MAX_FREQ_RANGE                  ( MAX_FREQ_RANGE                    ),
       .CHANNEL_SUPPORT                 ( CHANNEL_SUPPORT                   ),
       .MAX_PC_PAYLOAD_SIZE_RANGE       ( MAX_PC_PAYLOAD_SIZE_RANGE         ),
       .MAX_PC_READREQ_SIZE_RANGE       ( MAX_PC_READREQ_SIZE_RANGE         ),
       .MAX_OOB_PAYLOAD_SIZE_RANGE      ( MAX_OOB_PAYLOAD_SIZE_RANGE        ),
       .MAX_VW_COUNT_SUPPORTED          ( MAX_VW_COUNT_SUPPORTED            ),
       .TABLE_VERSION                   ( TABLE_VERSION                     )
       )
   vgpio_espi_wrapper
     (
      .clk                              ( wClk_100M                         ),
      .reset_n                          ( wRst_n                            ),
      // espi io
      .spi_clk                          ( CLK_66M_ESPI_CPU0_FPGA_R_LVC18         ),
      .spi_reset_n                      ( RST_ESPI_CPU0_FPGA_R_LVC18_N           ),
      .spi_cs_n                         ( ESPI_CPU0_CS1_FPGA_R2_LVC18_N          ),
      .spi_data_in                      ( espi_data_in                           ),
      .spi_data_out                     ( espi_data_out                          ),
      .spi_alert_n                      ( wIRQ_ESPI_CPU0_ALERT1_FPGA_LVC18_N     ),
      // Platform registers
      .plt_csr0                         ( table_version[7:0]                     ),
      .plt_csr1                         ( table_version[15:8]                    ),
      .plt_csr2                         ( table_version[23:16]                   ),
      .plt_csr3                         ( table_version[31:24]                   ),
      .plt_csr4                         ( plt_csr4                               ),
      .plt_csr5                         ( plt_csr5                               ),
      .plt_csr6                         ( plt_csr6                               ),
      .plt_csr7                         ( plt_csr7                               ),
      .plt_csr8                         ( plt_csr8                               ),
      .plt_csr9                         ( plt_csr9                               ),
      .plt_csra                         ( plt_csra                               ),
      .plt_csrb                         ( plt_csrb                               ),
      .plt_csrc                         ( plt_csrc                               ),
      .plt_csrd                         ( plt_csrd                               ),
      .plt_csre                         ( plt_csre                               ),
      .plt_csrf                         ( plt_csrf                               ),
       .nmi_n                           (  wCpuIrqNmiEspi_SyncESPI               ),
      // AVC cpufpga vgpio fixed assignments
      // GPO from master to slave
      .FM_UPI_INIT_DONE                 ( wUPI_INIT_DONE                    ),
      .FM_ADR_MODE0                     ( wFM_ADR_MODE0                     ),
      .FM_PERST_DELAY_SEL               (                                   ),
      // GPI from slave to master
      .FM_PASSWORD_CLEAR_N              ( wFM_PASSWORD_CLEAR_LVC25_N             ),
	  .PWRGD_AUX_PWRGD_CPU0_PLD         ( wPwrgdCpu0PltAuxPwrgdFpga_SyncESPI     ),
      .FM_BOARD_SKU_ID0                 ( FM_BOARD_SKU_ID0                       ),
      .FM_BOARD_SKU_ID1                 ( FM_BOARD_SKU_ID1                       ),
      .FM_BOARD_SKU_ID2                 ( FM_BOARD_SKU_ID2                       ),
      .FM_BOARD_SKU_ID3                 ( FM_BOARD_SKU_ID3                       ),
      .FM_BOARD_SKU_ID4                 ( FM_BOARD_SKU_ID4                       ),
      .FM_BOARD_SKU_ID5                 ( FM_BOARD_SKU_ID5                       ),
      .RES_147_2                        ( 1'b1                                   ),
      .RES_147_3                        ( 1'b1                                   ),
      .FM_BOARD_REV_ID0                 ( FM_BOARD_REV_ID0                       ),
      .FM_BOARD_REV_ID1                 ( FM_BOARD_REV_ID1                       ),
      .FM_BOARD_REV_ID2                 ( FM_BOARD_REV_ID2                       ),
      .FM_RST_PERST_BIT0                ( wFM_RST_PERST_BIT0_LVC25               ),// spare input
      .FM_RISER2_WIDTH                  ( FM_CPU0_LEFT_RISER_WIDTH_LVC18         ),
      .FM_RISER2_MODE                   ( FM_CPU0_LEFT_RISER_MODE_LVC18_N        ),
      .FM_RISER3_WIDTH                  ( FM_CPU1_RIGHT_RISER_WIDTH_LVC18        ),
      .FM_RISER3_MODE                   ( FM_CPU1_RIGHT_RISER_MODE_LVC18_N       ),
      .FM_CPU0_INTR_PRSNT_N             ( wCpu0IntrPrsnt_n_SyncESPI              ),// INTR PRSNT signal (qualified with SKTOCC, PROC_ID and IntrpsrCablePrsnt) for CPU0
      .FM_CPU1_INTR_PRSNT_N             ( wCpu1IntrPrsnt_n_SyncESPI              ),// INTR PRSNT signal (qualified with SKTOCC, PROC_ID and IntrpsrCablePrsnt) for CPU1
      .FM_CPU0_INTR_ID                  ( wCpu0IntrTypeABn_SyncESPI              ),// on BNC, (A->1 and B->0)
      .FM_CPU1_INTR_ID                  ( wCpu1IntrTypeABn_SyncESPI              ),// on BNC, (A->1 and B->0)
      .FM_PCIE_EV_BIF_EN                ( wFmPcieFvBifEn_SyncESPI            ),// from dip-switch
      .H_CPU0_ERR0_LVC1_N               ( H_CPU0_ERR0_FPGA_LVC1_R_N              ),
      .FM_SFFX4_EXPCARD_IO_B_0          ( FM_CPU0_EDSFFX4_EXPCARD_IO0_LVC3_R     ),// should not be in/out, input only
      // espi config
      .device_id_reg                    ( device_id_reg                          ),
      .general_config_reg               ( general_config_reg                     ),
      .channel0_config_reg              ( channel0_config_reg                    ),
      .channel1_config_reg              ( channel1_config_reg                    ),
      .channel2_config_reg              ( channel2_config_reg                    ),
      .channel3_config_reg              ( channel3_config_reg                    )
      );

 assign wCPU_IRQ_NMI_ESPI       = wNMI_SEL_CPU_eSPI ? 1'b0 : wIRQ_BMC_CPU_NMI_P0;// if nmi_sel is 0 nmi signal of front panel go to espi

 assign H_CPU0_NMI_LVC1_FPGA_R  = wNMI_SEL_CPU_eSPI && wPwrgdPvnnMainCpu0_SyncLvds ? wIRQ_BMC_CPU_NMI_P0 : 1'b0;// if nmi_sel is 1 nmi signal of front pane1 go to irq cpu pin
 
 assign H_CPU1_NMI_LVC1         = wPWRGD_PVNN_MAIN_CPU1_FF ? (wInModular ? 1'bZ : 1'b0) : 1'bZ;

   //END OF ESPI
   //------------------------------------------------------------------------------------------------------   


   // using internal PLL to generate internal clock and reset signals from external 25MHz clock input
   pll_cpu pll_main_inst
     (
      .areset ( !PWRGD_P1V2_MAX10_AUX_PLD_R_LVC3 ), // PWRGD for last PLD VR is used as the reset signal for the PLL (active low, hence inverted)
      .inclk0 ( CLK_25M_OSC_MAIN_FPGA_LVC3       ), // input clock from external source @ 25 MHz
      .c0     ( wClk_2M                          ), // 2  MHz
      .c1     ( wClk_20M                         ), // 20 MHz
      .c2     ( wClk_100M                        ), // 100 MHz
      .c3     ( wClk_25M                         ), // 25 MHz
	  .c4     ( wClk_50M                         ), // 50 MHz
      .locked ( wDRst_n                          )
      );

   delay #(.COUNT(2000))
     Timer1(
               .iClk    ( wClk_2M ),
               .iRst    ( wDRst_n ),
               .iStart  ( wDRst_n ),
               .iClrCnt ( 1'b0    ),
               .oDone   ( wRst_n  )
               );
   
   

   //PLL for ADC usage
   //As ADC data is sent thru LVDS, to avoid Clock Crossing Domain (CCD) issue, we use lvds signal
   pll_adc	pll_adc_inst 
     (
	  .inclk0 (  wTxCoreClk    ),
	  .c0     (  wClk_2M_adc   ),
	  .c1     (  wClk_25M_adc  ),
	  .locked (  wAdcPllLocked )
	  );

   assign wFM_SMB_BMC_NVME_LVC3_ALERT_N = 1'b1;

   // Synchronize to 2MHz clock domain

   InputsSyncWithDefault #
     (
      .SIZE       (27 ),
      .DEFAULT_OUT( 27'b011_0_0000_0010_0000_0000_0000_000 )
      ) InputsSyncWithDefault_2M
       (
        .i_Clk  ( wClk_2M ),
        .i_Rst_n( wRst_n ),
        .i_vSync({
		          wMBVR_ready_ack, // MBVR flow for Modular
		          wFM_CPU0_PWRBTN_FPGA_R_LVC18_N,
                  wRST_CPU0_RSTBTN_FPGA_LVC18_R_N,
		          
				  wFM_HPFR_OUT, // HPFR.
                  wMcsiAligned,
                  wCpu1IntrClkConfDone,
                  wAUX_PWRGD_CPU0_SCM,
                  wAUX_PWRGD_CPU1_SCM,                    //0000

                  wFmCpu0IntrpsrCablePrsnt,
                  wFmCpu1IntrpsrCablePrsnt,
                  wFM_BMC_ONCTL_N,
                  wSCM_BMC_AUX_PWR_OK,                    //0010

                  wSCM_BMC_AUX_PWR_FAULT,
                  wSURPRISE_RESET,
                  wFM_GLOBAL_RESET,
                  PWRGD_P1V0_AUX,                         //0000

                  PWRGD_P1V1_AUX,
                  RST_CPU0_PLTRST_SYNC_FPGA_LVC18_R_N,
                  RST_PLTRST_CPU1_PLD_R_LVC1_N,
                  force_to_enter_err,                     //0000

                  wLegacyNode,
                  wGLBRST_HOLD_OFF_EN,
                  wGLBRST_HOLD_OFF,
                  wFM_GLBRST_HALT_MODE,                   //0000

                  PWRGD_P1V2_MAX10_AUX_PLD_R_LVC3,
                  rjo_ready,
                  wSMRJODone                              //000
                  }),
        .o_vSync({
		          wMbvrReadyAckSync2M,  // MBVR flow for Modular
		          wFmCpu0PwrbtnFpgaSync2M_n,
                  wFmRstCpu0RstBtnFpgaSync2M_n,
				  
				  wFmHpfrOut_sync2M, // HPFR.
                  wMcsiAlignedSync2M,
                  wCpu1IntrClkConfDoneSync2M,
                  wAuxPwrGdCpu0ScmSync2M,
                  wAuxPwrGdCpu1ScmSync2M,
                  wFmCpu0IntrpsrCablePrsntSync2M,
                  wFmCpu1IntrpsrCablePrsntSync2M,
                  wBmcOnctlSync2M,
                  wScmBmcAuxPwrOKSync2M,
                  wScmBmcAuxPwrFaultSync2M,
                  wSurpriseResetSync2M,
                  wGlobalResetSync2M,
                  wPwrGdP1V0AuxSync2M,
                  wPwrGdP1V1AuxSync2M,
                  wRstCpu0PltrstSyncFpgaSync2M_n,
                  wRstPltrstCpu1PldSync2M_n,
                  wForceToEnterErrSync2M,
                  wLegacyNodeSync2M,
                  wGlbRstHoldOffEnaSync2M,
                  wGlbRstHoldOffSync2M,
                  wGlbRstHaltModeSync2M,
                  wPwrGdP1V2Max10AuxSync2M,
                  wRjoReadySync2M,
                  wRjoReadySecSync2M
                  })
        );
   //Synchronizer/Glitchfilter for signals to be sent directly thru LVDS I/F
   GlitchFilter2 #(.NUMBER_OF_SIGNALS(LVDS_REGS),
				   .RST_VALUE(
										66'b000_000_0101_1011_1000_0011_0110_1100_0000_0011_1111_1111_1110_1001_1111_1111_1100)
                   )
     lvds_filtering
       (
        .iClk(wTxCoreClk),
        .iARst_n(Reset_N),
        .iSRst_n(1'b1),
        .iEna(1'b1),
        .iSignal
        ({
		  
		  wPfrGlobalAck_toLVDS, // HPFR.
		  wLegacyNode_toLVDS,   // HPFR.
		  wHPfrEna,//_toLVDS,      // HPFR.   
		
		  wPWRGD_PVNN_MAIN_CPU0_FF,//59 //4'b0101
          //////////////////
		  wRST_PLTRST_CPU0_TPM_PLD_LVC18_N,
		  wPWRGD_CPU0_PLT_AUX_PWRGD_FPGA_LVC18_R,
          wFM_CPU0_SKTOCC_LVT3_PLD_N,
		  
		  wFM_CPU1_SKTOCC_LVT3_PLD_N,//55 //4'b1011
          wCPU1_AUX_PWR_OK,
          wH_CPU1_THERMTRIP_LVC1_N,
          wH_CPU0_MEMTRIP_LVC1_N,
          
		  wH_CPU0_THERMTRIP_LVC1_N,//51 //4'b1000
          wCpu1RmcaEncode,
          wCpu1CatErrEncode,
          wCpu0RmcaEncode,
          
		  wCpu0CatErrEncode,//47 //4'b0011
          FM_1200VA_OC,
          wFM_SLPS3_CPU1_CPU_PLD_N,
          wFM_SLPS4_CPU1_CPU_PLD_N,

          wPWRGD_CPU0_LVC1_R,//43 //4'b0110
          wFM_SLPS3_CPU0_CPU_PLD_N,
          wFM_SLPS4_CPU0_CPU_PLD_N,
          wFM_CPU0_GPIO4_EAF_BMC_SAFS_SEL_LVC1_RJO,

          wFM_BIOS_IMAGE_SWAP_N,//39 //4'b1100
          wVAL_DBG_JUMPER_EN_N,
          wCPU_AUX_PWR_FLT,
          wP3V3_FAULT,

          wPSU_FAULT,//35  //4'b0000
          wCPU_PWR_FLT,
          wMEM_PWR_FLT,
          wCPU_MISMATCH,

          PWRGD_CPU0_S0_PWROK_LVC1_R,//31           //4'b0011
          //////////////////
          PWRGD_PS_PWROK_R2,   
          H_CPU1_ERR2_FPGA_LVC1_N         || !PWRGD_CPU1_FPGA_LVC1,
          H_CPU1_ERR1_FPGA_LVC1_N         || !PWRGD_CPU1_FPGA_LVC1,

          H_CPU1_ERR0_FPGA_LVC1_N         || !PWRGD_CPU1_FPGA_LVC1,//27  4'b1111  
          H_CPU1_MEMHOT_OUT_LVC1_R2_N     || !PWRGD_CPU1_FPGA_LVC1,
          wH_CPU1_MEMTRIP_LVC1_R2_N       || !PWRGD_CPU1_FPGA_LVC1,          //4'b1111 
          wH_CPU1_THERMTRIP_LVC1_R2_N     || !PWRGD_CPU1_FPGA_LVC1,        
          
		  H_CPU0_MON_FAIL_PLD_LVC1_N      || !wPWRGD_CPU0_LVC1_R,//23     //4'b1111
          H_CPU0_ERR2_FPGA_LVC1_R_N       || !wPWRGD_CPU0_LVC1_R,
          H_CPU0_ERR1_FPGA_LVC1_R_N       || !wPWRGD_CPU0_LVC1_R,           
          H_CPU0_ERR0_FPGA_LVC1_R_N       || !wPWRGD_CPU0_LVC1_R,  
          
		  H_CPU0_MEMHOT_OUT_LVC1_FPGA_N   || !wPWRGD_CPU0_LVC1_R, //19 //4'b1110  
          H_CPU0_MEMTRIP_LVC1_FPGA_N      || !wPWRGD_CPU0_LVC1_R,     
          wH_CPU0_THERMTRIP_FPGA_LVC1_R_N || !wPWRGD_CPU0_LVC1_R,      
          wFM_ASD_EN_DET_LVC3,

          FM_DBP_POD_PRSNT_N,//15    //4'b1001
          FM_S3M_CPU1_CPLD_CRC_ERROR_LVC3  && PWRGD_CPU1_FPGA_LVC1,
          FM_S3M_CPU0_CPLD_CRC_ERROR_LVC3  && wPWRGD_CPU0_LVC1_R,        
          IRQ_CPU1_MEM_VRHOT_LVC25_N,

          IRQ_CPU0_MEM_VRHOT_LVC25_N,//11        //4'b1111
          IRQ_CPU1_VRHOT_LVC25_N,
          IRQ_CPU0_VRHOT_LVC25_N,                  
          IRQ_SML1_PMBUS_PLD_ALERT_LVC3_N,

          wFM_SMB_BMC_NVME_LVC3_ALERT_N,//7           //4'b1111
          FP_NMI_BTN_N,
          FP_ID_BTN_LVC3_N,                    
          FP_RST_BTN_N,
		  
          FP_PWR_BTN_N,   //3'b1100
          H_CPU1_MON_FAIL_PLD_LVC1_N      || !PWRGD_CPU1_FPGA_LVC1,
          (RST_CPU1_PLTRST_SYNC_LVC18_N && !wFM_CPU1_SKTOCC_LVT3_PLD_N && wPWRGD_CPU0_LVC1_R),  
          (RST_CPU0_PLTRST_SYNC_LVC18_N && !wFM_CPU0_SKTOCC_LVT3_PLD_N && wPWRGD_CPU0_LVC1_R) 
          }),
        .oFilteredSignals
        ({
		  wFmHpfrInSyncLvds,
		  wFmLegacySyncLvds,
		  wFmHpfrActive,    
		
		  
		  wPwrgdPvnnMainCpu0_SyncLvds,//59 //4'b0101
		  wRstPltrstCpu0TpmPld_n_RJOSync,
          wPwrgdCpu0PltAuxPwrgdFpga_RJOSync,
          wFmCpu0sktoccPld_nSyncLvds,

		  wFmCpu1sktoccPld_nSyncLvds,//55 //4'b1011
          ///////////////////////
          wCpu1AuxPwrOkSyncLvds,
          wCpu1ThermtripSyncLvds_n,
          wCpu0MemtripSyncLvds_n,

          wCpu0ThermtripSyncLvds_n,//51 //4'b1000
          wCpu1RmcaEncodeSyncLvds,
          wCpu1CatErrEncodeSyncLvds,
          wCpu0RmcaEncodeSyncLvds,

          wCpu0CatErrEncodeSyncLvds,//47 //4'b0011
          w1200VaOCSyncLvds,
          wSlpS3Cpu1SyncLvds_n,
          wSlpS4Cpu1SyncLvds_n,

          wPwrGdCpu0SyncLvds,//43 //4'b0110
          wSlpS3Cpu0SyncLvds_n,
          wSlpS4Cpu0SyncLvds_n,
          wCpu0Gpio4EafBmcSafsSelSyncLvds,

          wBiosImageSwapSyncLvds_n,//39 //4'b1100
          wValDbgJumperEnSyncLvds_n,
          wCpuAuxPwrFltSyncLvds,
          wP3V3FaultSyncLvds,
          
		  wPsuFaultSyncLvds,//35  //4'b0000
          wCpuPwrFltSyncLvds,
          wMemPwrFltSyncLvds,
          wCpuMismatchSyncLvds,
		  
          wPwrGdCpu0S0PwrOkSyncLvds,//31           //4'b0011

          ///////////////////////

          wPWRGD_PS_PWROK_CPU_PLD_R, 
          wCpu1Err2_n_FF,
          wCpu1Err1_n_FF,
		  
          wCpu1Err0_n_FF, //27  4'b1111
          wCpu1MemHotOut_n_FF,
          wCpu1Memtrip_n_FF,
          wCpu1Thermtrip_n_FF,

          wCpu0MonFail_n_FF,//23     //4'b1111
          wCpu0Err2_n_FF,
          wCpu0Err1_n_FF,
		  wCpu0Err0_n_FF,
          
		  wCpu0MemHotOut_n_FF,//19 //4'b1110
          wCpu0Memtrip_n_FF,
          wCpu0Thermtrip_n_FF,
          wASDEnDet,
		  
          wDbpPodPrsnt_n_FF,//15    //4'b1001
          wS3MCpu1CpldCrcError_FF,
          wS3MCpu0CpldCrcError_FF,
          wIrqCpu1MemVrHot_n_FF,
		  
          wIrqCpu0MemVrHot_n_FF,//11        //4'b1111
          wIrqCpu1VrHot_n_FF,
          wIrqCpu0VrHot_n_FF,
          wIrqSml1PmbusAlert_n_FF,
		  
          wFmSmbBmcNvmeAlert_n_FF,//7           //4'b1111
          wFpNmiBtn_n_FF,
          wFpIdBtn_n_FF,
          wFpRstBtn_n_FF,
		  
          wFpPwrBtn_n_FF,  //3'b1100
          wCpu1MonFail_n_FF,
          wRstCpu1PltrstSync_FF,
          wRstCpu0PltrstSync_FF
          })
        );
wire force_pwron_sync;
level_sync sync_force (.clk(wClk_2M), .signal_in(FM_FORCE_PWRON_LVC18 ), .signal_sync(force_pwron_sync));   

   //Platform Logic main
   beechnut_city_main
     #(
       .FPGA_REV                            (`MAIN_MAJOR_VERSION),
       .FPGA_REV_TEST                       (`MAIN_MINOR_VERSION)
       )
   beechnut_city_main_inst
     (
      //Input CLK
      .iClk_2M                              (wClk_2M),
      .iClk_20M                             (wClk_20M),
      .iClk_100M                            (wClk_100M),
      .iRST_N                               (wRst_n),
      .iLTPI_LINK_ALIGNED                   (wMcsiAlignedSync2M), //Sync2M
      .PWRGD_P3V3_AUX                       (1'b1),
      .PWRGD_P1V8_AUX                       (1'b1),
      .PWRGD_P5V_AUX                        (1'b1),
      //SYS_CHECK
      .FM_CPU1_SKTOCC_LVT3_PLD_N            (wFM_CPU1_SKTOCC_LVT3_PLD_N),
      .FM_CPU0_SKTOCC_LVT3_PLD_N            (wFM_CPU0_SKTOCC_LVT3_PLD_N),
      .FM_CPU0_PROC_ID1                     (FM_CPU0_PROC_ID1),
      .FM_CPU0_PROC_ID0                     (FM_CPU0_PROC_ID0),
      .FM_CPU1_PROC_ID1                     (FM_CPU1_PROC_ID1),
      .FM_CPU1_PROC_ID0                     (FM_CPU1_PROC_ID0),
      .FM_CPU0_PKGID2                       (wFM_CPU0_PKGID2),
      .FM_CPU0_PKGID1                       (wFM_CPU0_PKGID1),
      .FM_CPU0_PKGID0                       (wFM_CPU0_PKGID0),
      .FM_CPU1_PKGID2                       (wFM_CPU1_PKGID2),
      .FM_CPU1_PKGID1                       (wFM_CPU1_PKGID1),
      .FM_CPU1_PKGID0                       (wFM_CPU1_PKGID0),

      .iCpu1IntrClkConfDone                 (wCpu1IntrClkConfDoneSync2M),

      .iAUX_PWRGD_CPU0_SCM                  (wAuxPwrGdCpu0ScmSync2M),              //from SCM FPGA thru LVDS
      .iAUX_PWRGD_CPU1_SCM                  (wAuxPwrGdCpu1ScmSync2M),              //from SCM FPGA thru LVDS
      .iIBL_RDY_N                           (rIblRdySync2M_n),  //from DBG PLD thru sGPIO
      .iFM_CPU0_INTR_PRSNT_N                (!wFmCpu0IntrpsrCablePrsntSync2M),            //from DBG PLD thru sGPIO
      .iFM_CPU1_INTR_PRSNT_N                (!wFmCpu1IntrpsrCablePrsntSync2M),            //from DBG PLD thru sGPIO
      .oCPU1_AUX_PWR_OK                     (wCPU1_AUX_PWR_OK),
      .oCPU_AUX_PWR_FLT                     (wCPU_AUX_PWR_FLT),                 ////To DBG PLD thru sGPIO
      .oCPU0_AUX_PWR_OK                     (wCPU0_AUX_PWR_OK),
      .oCPU_MISMATCH                        (wCPU_MISMATCH),
      //VR BYPASS
      .iFM_FORCE_PWRON_LVC18                (force_pwron_sync),
      .oLED_STATUS                          (wLED_STATUS),                      //To DBG PLD thru sGPIO
      //DC-SCM
      .iBMC_ONCTL_N                         (wBmcOnctlSync2M),                   //from SCM FPGA thru LVDS
      .iSCM_BMC_Done                        (wScmBmcAuxPwrOKSync2M),              //from SCM FPGA thru LVDS
      .iSCM_BMC_FLT                         (wScmBmcAuxPwrFaultSync2M),                      //from SCM FPGA thru LVDS
      //PSU CONTROL
      .FM_S5_WITH_12V_N                     (wS5With12V_n),
      .PWRGD_PS_PWROK_CPU_PLD_R             (PWRGD_PS_PWROK_R2),
      .PWRGD_P3V3                           (PWRGD_P3V3_LVC25_PWRGD),
      .oPSU_FLT_CODE                        (wPSU_FLT_CODE),                    //To DBG FPGA via sGPIO
      .oFM_PLD_CLKS_DEV_R_EN                (FM_PLD_CLKS_DEV_LVC3_R_EN),
      .oPSU_FAULT                           (wPSU_FAULT),
      .oP3V3_FAULT                          (wP3V3_FAULT),

      .iSURPRISE_RESET                      (wSurpriseResetSync2M),

      .iFM_GLOBAL_RESET                     (wGlobalResetSync2M),

      //VR ENABLE
      .FM_P3V3_EN                           (FM_P3V3_LVC25_EN),
      .FM_P1V0_AUX_EN                       (FM_P1V0_AUX_LVC18_EN),
      .FM_P1V1_AUX_EN                       (FM_P1V1_AUX_LVC18_EN),
      .FM_PS_EN_R                           (wFM_PS_EN_PLD_R_LVC3),
      .FM_AUX_SW_EN                         (FM_AUX_SW_LVC3_EN),
      .FM_P5V_EN                            (FM_P5V_EN),
      .FM_P12V_DIMM_PCIE_SW_CPU0_EN         (FM_DIMM_PCIE_CPU0_SW_P12V_LVC3_R_EN),
      .FM_P12V_DIMM_PCIE_SW_CPU1_EN         (FM_DIMM_PCIE_CPU1_SW_P12V_LVC3_R_EN),
      //CPU ERROR CODe
      .oCPU0_FLT_CODE                       (wCPU0_FLT_CODE),                   //To DBG FPGA via sGPIO
      .oCPU1_FLT_CODE                       (wCPU1_FLT_CODE),                   //To DBG FPGA via sGPIO
      //MEM ERROR CODe
      .oCPU0_DIMM_FLT_CODE                  (wCPU0_DIMM_FLT_CODE),         //To DBG FPGA via sGPIO
      .oCPU1_DIMM_FLT_CODE                  (wCPU1_DIMM_FLT_CODE),         //To DBG FPGA via sGPIO
      //CPU0 VR enable
      .FM_PVCCFA_EHV_CPU0_R_EN              (FM_PVCCFA_EHV_CPU0_R_LVC25_EN),
      .FM_PVNN_MAIN_CPU0_R_EN               (FM_PVNN_AUX_CPU0_EN_R_LVC25),
      .FM_PVCCD_HV_CPU0_R_EN                (FM_PVCCD_HV_CPU0_EN_R_LVC25),
      .FM_PVCCFA_EHV_FIVRA_CPU0_R_EN        (FM_PVCCFA_EHV_FIVRA_CPU0_R_LVC25_EN),
      .FM_PVCCINFAON_CPU0_R_EN              (FM_PVCCINFAON_CPU0_R_LVC25_EN),
      .FM_PVCCIN_CPU0_R_EN                  (FM_PVCCIN_CPU0_R_LVC25_EN),
      //CPU1 VR enable
      .FM_PVCC3V3_AUX_CPU1_EN               (FM_CPU1_PVCC3V3_AUX_EN_LVC3_R),
      .FM_PVCCFA_EHV_CPU1_R_EN              (FM_PVCCFA_EHV_CPU1_LVC3_R_EN),
      .FM_PVNN_MAIN_CPU1_R_EN               (FM_PVNN_AUX_CPU1_LVC3_R_EN),
      .FM_PVCCD_HV_CPU1_R_EN                (FM_PVCCD_HV_CPU1_LVC3_R_EN),
      .FM_PVCCFA_EHV_FIVRA_CPU1_R_EN        (FM_PVCCFA_EHV_FIVRA_CPU1_LVC3_R_EN),
      .FM_PVCCINFAON_CPU1_R_EN              (FM_PVCCINFAON_CPU1_LVC3_R_EN),
      .FM_PVCCIN_CPU1_R_EN                  (FM_PVCCIN_CPU1_R_LVC18_EN),
      //AUX
      .iPWRGD_P1V0_AUX                      (wPwrGdP1V0AuxSync2M),             
      .iPWRGD_P1V1_AUX                      (wPwrGdP1V1AuxSync2M),             
      //CPU
      .FM_SLPS3_CPU0_CPU_PLD_N              (1'b1),
      .FM_SLPS4_CPU0_CPU_PLD_N              (FM_CPU0_SLPS4_FPGA_R_LVC18_N),
      .FM_SLPS3_CPU1_CPU_PLD_N              (FM_CPU1_SLPS3_LVC18_N),
      .FM_SLPS4_CPU1_CPU_PLD_N              (FM_CPU1_SLPS4_LVC18_N),
      .PWRGD_PVCCFA_EHV_CPU0                (PWRGD_PVCCFA_EHV_CPU0_LVC25_PWRGD),
      .PWRGD_PVNN_MAIN_CPU0                 (PWRGD_PVNN_MAIN_CPU0_LVC25_PWRGD),
      .PWRGD_PVCCD0_HV_CPU0                 (PWRGD_PVCCD0_HV_CPU0_LVC25_PWRGD),
      .PWRGD_PVCCD1_HV_CPU0                 (PWRGD_PVCCD1_HV_CPU0_LVC25_PWRGD),
      .PWRGD_PVCCFA_EHV_FIVRA_CPU0          (PWRGD_PVCCFA_EHV_FIVRA_CPU0_LVC25),
      .PWRGD_PVCCINFAON_CPU0                (PWRGD_PVCCINFAON_CPU0_LVC25_PWRGD),
      .PWRGD_PVCCIN_CPU0                    (PWRGD_PVCCIN_CPU0_LVC25_PWRGD),
      .FM_CPU0_GLB_RST_WARN_PLD_N           (FM_CPU0_GLB_RST_WARN_FPGA_LVC18_N_R),
      .PWRGD_PVCCFA_EHV_CPU1                (PWRGD_PVCCFA_EHV_CPU1_LVC25_PWRGD),
      .PWRGD_PVNN_MAIN_CPU1                 (PWRGD_PVNN_MAIN_CPU1_LVC25_PWRGD),
      .PWRGD_PVCCD0_HV_CPU1                 (PWRGD_PVCCD0_HV_CPU1_LVC25_PWRGD),
      .PWRGD_PVCCD1_HV_CPU1                 (PWRGD_PVCCD1_HV_CPU1_LVC25_PWRGD),
      .PWRGD_PVCCFA_EHV_FIVRA_CPU1          (PWRGD_PVCCFA_EHV_FIVRA_CPU1_LVC25_PWRGD),
      .PWRGD_PVCCINFAON_CPU1                (PWRGD_PVCCINFAON_CPU1_LVC25_PWRGD),
      .PWRGD_PVCCIN_CPU1                    (PWRGD_PVCCIN_CPU1_LVC25_PWRGD),
      .FM_CPU1_GLB_RST_WARN_PLD_N           (FM_CPU1_GLB_RST_WARN_LVC18_N),
      .FM_CPU0_REFCLK_RDY_PLD               (FM_CPU0_REFCLK_RDY_R_FPGA_LVC18_OD),
      .FM_CPU1_REFCLK_RDY_PLD               (FM_CPU1_REFCLK_RDY_R_FPGA_LVC18),
      .PWRGD_AUX_PWRGD_CPU0_PLD             (wPWRGD_CPU0_PLT_AUX_PWRGD_FPGA_LVC18_R),
      .PWRGD_AUX_PWRGD_CPU1_PLD             (PWRGD_CPU1_PLT_AUX_PWRGD_FPGA_LVC18),
      .PWRGD_S0_PWROK_CPU0_R                (PWRGD_CPU0_S0_PWROK_LVC1_R),
      .PWRGD_S0_PWROK_CPU1_R                (PWRGD_CPU1_S0_PWROK_LVC1_R),
      .PWRGD_CPU0_LVC1_R                    (PWRGD_CPU0_FPGA_LVC1),
      .PWRGD_CPU1_LVC1_R                    (PWRGD_CPU1_FPGA_LVC1),
      .FM_S5_PWR_RETAINED_CPU0_PLD          (FM_CPU0_S5_PWR_RETAINED_FPGA_R),
      .RST_CPU0_RESET_R_N                   (RST_CPU0_LVC1_R_N),
      .RST_CPU1_RESET_R_N                   (RST_CPU1_LVC1_R_N),
      .iRST_PLTRST_CPU0_PFR_LVC3_N          (RST_PLTRST_CPU0_PLD_LVC18_N),
      .iRST_PLTRST_CPU1_PFR_LVC3_N          (wRstPltrstCpu1PldSync2M_n),
      //MEM
      .M_AB_CPU0_RESET_N                    (M_AB_CPU0_RESET_LVC1_N),
      .M_CD_CPU0_RESET_N                    (M_CD_CPU0_RESET_LVC1_N),
      .M_EF_CPU0_RESET_N                    (M_EF_CPU0_RESET_LVC1_N),
      .M_GH_CPU0_RESET_N                    (M_GH_CPU0_RESET_LVC1_N),

      .M_AB_CPU1_RESET_N                    (M_AB_CPU1_RESET_LVC1_N),
      .M_CD_CPU1_RESET_N                    (M_CD_CPU1_RESET_LVC1_N),
      .M_EF_CPU1_RESET_N                    (M_EF_CPU1_RESET_LVC1_N),
      .M_GH_CPU1_RESET_N                    (M_GH_CPU1_RESET_LVC1_N),

      .PWRGD_FAIL_CPU0_AB_PLD               (PWRGD_FAIL_CPU0_AB_PLD_LVC3),
      .PWRGD_FAIL_CPU0_CD_PLD               (PWRGD_FAIL_CPU0_CD_PLD_LVC3),
      .PWRGD_FAIL_CPU0_EF_PLD               (PWRGD_FAIL_CPU0_EF_PLD_LVC3),
      .PWRGD_FAIL_CPU0_GH_PLD               (PWRGD_FAIL_CPU0_GH_PLD_LVC3),

      .PWRGD_FAIL_CPU1_AB_PLD               (PWRGD_FAIL_CPU1_AB_PLD_LVC3),
      .PWRGD_FAIL_CPU1_CD_PLD               (PWRGD_FAIL_CPU1_CD_PLD_LVC3),
      .PWRGD_FAIL_CPU1_EF_PLD               (PWRGD_FAIL_CPU1_EF_PLD_LVC3),
      .PWRGD_FAIL_CPU1_GH_PLD               (PWRGD_FAIL_CPU1_GH_PLD_LVC3),

      .PWRGD_DRAMPWRGD_CPU0_AB_R_LVC1       (PWRGD_DRAMPWRGD_CPU0_AB_R_LVC1),
      .PWRGD_DRAMPWRGD_CPU0_CD_R_LVC1       (PWRGD_DRAMPWRGD_CPU0_CD_R_LVC1),
      .PWRGD_DRAMPWRGD_CPU0_EF_R_LVC1       (PWRGD_DRAMPWRGD_CPU0_EF_R_LVC1),
      .PWRGD_DRAMPWRGD_CPU0_GH_R_LVC1       (PWRGD_DRAMPWRGD_CPU0_GH_R_LVC1),

      .PWRGD_DRAMPWRGD_CPU1_AB_R_LVC1       (PWRGD_DRAMPWRGD_CPU1_AB_R_LVC1),
      .PWRGD_DRAMPWRGD_CPU1_CD_R_LVC1       (PWRGD_DRAMPWRGD_CPU1_CD_R_LVC1),
      .PWRGD_DRAMPWRGD_CPU1_EF_R_LVC1       (PWRGD_DRAMPWRGD_CPU1_EF_R_LVC1),
      .PWRGD_DRAMPWRGD_CPU1_GH_R_LVC1       (PWRGD_DRAMPWRGD_CPU1_GH_R_LVC1),

      .M_AB_CPU0_FPGA_RESET_R_N             (M_AB_CPU0_FPGA_RESET_R_LVC1_N),
      .M_CD_CPU0_FPGA_RESET_R_N             (M_CD_CPU0_FPGA_RESET_R_LVC1_N),
      .M_EF_CPU0_FPGA_RESET_R_N             (M_EF_CPU0_FPGA_RESET_R_LVC1_N),
      .M_GH_CPU0_FPGA_RESET_R_N             (M_GH_CPU0_FPGA_RESET_R_LVC1_N),

      .M_AB_CPU1_FPGA_RESET_R_N             (M_AB_CPU1_FPGA_RESET_R_LVC1_N),
      .M_CD_CPU1_FPGA_RESET_R_N             (M_CD_CPU1_FPGA_RESET_R_LVC1_N),
      .M_EF_CPU1_FPGA_RESET_R_N             (M_EF_CPU1_FPGA_RESET_R_LVC1_N),
      .M_GH_CPU1_FPGA_RESET_R_N             (M_GH_CPU1_FPGA_RESET_R_LVC1_N),

      //PLT LOGic
      .FM_RST_PERST_BIT0                    (wFM_RST_PERST_BIT0_LVC25),
      .FM_RST_PERST_BIT1                    (wFM_RST_PERST_BIT1_LVC25),
      .FM_RST_PERST_BIT3                    (wFM_RST_PERST_BIT3_LVC25),
      .FM_PASSWORD_CLEAR_N                  (wFM_PASSWORD_CLEAR_LVC25_N),
      .IRQ_PMBUS_PLD_ALERT_N                (IRQ_SML1_PMBUS_PLD_ALERT_LVC3_N),
      .FM_SERIAL_BOOT                       (wFM_SERIAL_BOOT),
      .FM_PERST_TIMING_SEL                  (wFM_PERST_TIMING_SEL),
      .H_CPU0_PROCHOT_LVC1_R_N              (wH_CPU0_PROCHOT_LVC1_R_N),
      .H_CPU1_PROCHOT_LVC1_R_N              (wH_CPU1_PROCHOT_LVC1_R_N),
      .H_CPU0_MEMHOT_IN_LVC1_R_N            (wH_CPU0_MEMHOT_IN_LVC1_R_N),
      .H_CPU1_MEMHOT_IN_LVC1_R_N            (wH_CPU1_MEMHOT_IN_LVC1_R_N),
      .FM_SYS_THROTTLE_R_N                  (wFM_SYS_THROTTLE_R_N),
      //ERROR
      .IRQ_CPU0_VRHOT_N                     (IRQ_CPU0_VRHOT_LVC25_N),
      .IRQ_CPU1_VRHOT_N                     (IRQ_CPU1_VRHOT_LVC25_N),
      .IRQ_CPU0_MEM_VRHOT_N                 (IRQ_CPU0_MEM_VRHOT_LVC25_N),
      .IRQ_CPU1_MEM_VRHOT_N                 (IRQ_CPU1_MEM_VRHOT_LVC25_N),
      .H_CPU0_CATERR_LVC1_N                 (H_CPU0_CATERR_LVC1_R2_N),
      .H_CPU0_RMCA_LVC1_N                   (H_CPU0_RMCA_LVC1_R2_N),
      .H_CPU1_CATERR_LVC1_N                 (H_CPU1_CATERR_LVC1_R2_N),
      .H_CPU1_RMCA_LVC1_N                   (H_CPU1_RMCA_LVC1_R2_N),
      .oH_CPU0_CATERR_LVC1_ENCODE           (wCpu0CatErrEncode),
      .oH_CPU0_RMCA_LVC1_ENCODE             (wCpu0RmcaEncode),
      .oH_CPU1_CATERR_LVC1_ENCODE           (wCpu1CatErrEncode),
      .oH_CPU1_RMCA_LVC1_ENCODE             (wCpu1RmcaEncode),
      //OCP NIC
      .PWRGD_OCP0_PWR                       (PWRGD_OCP_NIC_PWRGD),
      .FM_OCP0_CARD_PRSNTB_LVC3_N           (FM_CPU1_PE3_OCP_NIC_NVME14_PRSTN0_N),
      .o_FM_OCP_AUX_PWR_EN                  (FM_OCP_NIC_AUX_PWR_LVC3_R_EN),
      .o_FM_OCP_MAIN_PWR_EN                 (FM_OCP_NIC_MAIN_PWR_LVC3_R_EN),
      .o_FM_PLD_OCP_RBT_ISOLATE_N           (FM_PLD_OCP_NIC_RBT_ISOLATE_LVC3_N),
      .o_OcpPwrFlt_LED                      (w_OcpPwrFlt_LED),

      //EDSFF CARD
      .FM_M2_EDSFF_PRSNT_N                  (FM_CPU0_EDSFFX4_PRSNT0_LVC3_N),
      .FM_SFFX4_EXPCARD_IO_B_0              (FM_CPU0_EDSFFX4_EXPCARD_IO0_LVC3_R),
      //DC-SCM SPEC
      .FM_HPM_STBY_EN                       (FM_HPM_STBY_EN_LVC18),
      .FM_HPM_STBY_RST_N                    (wHpmStbyRst_n),
      .oFM_HPM_STBY_RDY                     (wFM_HPM_STBY_RDY_LVC18),
      .FM_SCM_PRSNT0_LVC3_N                 (FM_SCM_PRSNT0_LVC3_N),
      //ADR
      .FM_ADR_MODE0                         (wFM_ADR_MODE0),
      .FM_ADR_MODE1                         (1'b0),
      .FM_CPU0_ADR_TRIGGER_N                (iFM_CPU0_ADR_TRIGGER_N),
      .FM_CPU0_ADR_EXT_TRIGGER_N            (wFM_CPU0_ADR_EXT_TRIGGER_LVC25_N),
      .FM_CPU1_ADR_EXT_TRIGGER_N            (wFM_CPU1_ADR_EXT_TRIGGER_LVC25_N),
      .FM_ADR_COMPLETE_PLD                  (FM_CPU0_ADR_COMPLETE_FPGA_LVC18),
      .FM_ADR_COMPLETE_P1_PLD               (FM_CPU1_ADR_COMPLETE_LVC18),
      .oFM_CPU0_ADR_TRIGGER_N               (oFM_CPU0_ADR_TRIGGER_N),
      .ADRcounter1                          (ADRcounter1),
      .ADRcounter2                          (ADRcounter2),
      //Signals directly to LVDS, GlitchFilter'ed inside this module
      //CPU0 VNN
      .H_CPU0_THERMTRIP_LVC1_N              (wCpu0Thermtrip_n_FF),                        //to SCM FPGA thru LVDS
      .H_CPU0_MEMTRIP_LVC1_N                (wCpu0Memtrip_n_FF),                   //to SCM FPGA thru LVDS
      .H_CPU0_MEMHOT_OUT_LVC1_N             (H_CPU0_MEMHOT_OUT_LVC1_FPGA_N),             //to SCM FPGA thru LVDS
      .H_CPU0_ERR0_LVC1_N                   (H_CPU0_ERR0_FPGA_LVC1_R_N),                       //to SCM FPGA thru LVDS
      .H_CPU0_ERR1_LVC1_N                   (H_CPU0_ERR1_FPGA_LVC1_R_N),                       //to SCM FPGA thru LVDS
      .H_CPU0_ERR2_LVC1_N                   (H_CPU0_ERR2_FPGA_LVC1_R_N),                       //to SCM FPGA thru LVDS
      .H_CPU0_MON_FAIL_PLD_LVC1_N           (H_CPU0_MON_FAIL_PLD_LVC1_N),              //to SCM FPGA thru LVDS

      .oH_CPU0_THERMTRIP_LVC1_N             (wH_CPU0_THERMTRIP_LVC1_N),                //to SCM FPGA thru LVDS
      .oH_CPU0_MEMTRIP_LVC1_N               (wH_CPU0_MEMTRIP_LVC1_N),                    //to SCM FPGA thru LVDS

      //CPU1 VNN
      .H_CPU1_THERMTRIP_LVC1_N              (wCpu1Thermtrip_n_FF),                //to SCM FPGA thru LVDS
      .H_CPU1_MEMTRIP_LVC1_N                (wH_CPU1_MEMTRIP_LVC1_R2_N),                    //to SCM FPGA thru LVDS
      .H_CPU1_MEMHOT_OUT_LVC1_N             (H_CPU1_MEMHOT_OUT_LVC1_R2_N),              //to SCM FPGA thru LVDS
      .H_CPU1_ERR0_LVC1_N                   (H_CPU1_ERR0_FPGA_LVC1_N),                        //to SCM FPGA thru LVDS
      .H_CPU1_ERR1_LVC1_N                   (H_CPU1_ERR1_FPGA_LVC1_N),                        //to SCM FPGA thru LVDS
      .H_CPU1_ERR2_LVC1_N                   (H_CPU1_ERR2_FPGA_LVC1_N),                        //to SCM FPGA thru LVDS
      .H_CPU1_MON_FAIL_PLD_LVC1_N           (H_CPU1_MON_FAIL_PLD_LVC1_N),             //to SCM FPGA thru LVDS

      .oH_CPU1_THERMTRIP_LVC1_N             (wH_CPU1_THERMTRIP_LVC1_N),                 //to SCM FPGA thru LVDS

      .FM_SMB_BMC_NVME_LVC3_ALERT_N         (wFM_SMB_BMC_NVME_LVC3_ALERT_N),
      .FM_BOARD_SKU_ID0                     (FM_BOARD_SKU_ID0),
      .FM_BOARD_SKU_ID1                     (FM_BOARD_SKU_ID1),
      .FM_BOARD_SKU_ID2                     (FM_BOARD_SKU_ID2),
      .FM_BOARD_SKU_ID3                     (FM_BOARD_SKU_ID3),
      .FM_BOARD_SKU_ID4                     (FM_BOARD_SKU_ID4),
      .FM_BOARD_REV_ID0                     (FM_BOARD_REV_ID0),
      .FM_BOARD_REV_ID1                     (FM_BOARD_REV_ID1),
      .FM_BOARD_REV_ID2                     (FM_BOARD_REV_ID2),
      .FM_STANDALONE_MODE_N                 (wFM_STANDALONE_MODE_N),
      .FM_4S_8S_MODE_N                      (wFM_4S_8S_MODE_N),
      .FM_NODE_ID0                          (wFM_NODE_ID0),
      .FM_NODE_ID1                          (wFM_NODE_ID1),
      .FM_S3M_CPU0_CPLD_CRC_ERROR           (FM_S3M_CPU0_CPLD_CRC_ERROR_LVC3),
      .FM_S3M_CPU1_CPLD_CRC_ERROR           (FM_S3M_CPU1_CPLD_CRC_ERROR_LVC3),
      .FM_1200VA_OC                         (FM_1200VA_OC),
      .FM_BMC_SAFS_SEL                      (wFM_CPU0_GPIO4_EAF_BMC_SAFS_SEL_LVC1_LATCHED),
      .iFM_DUAL_PARTITION_N                 (wFM_DUAL_PARTITION_LVC3_N),
      .iFM_PARTITION_SEL                    (wFM_PARTITION_SEL_LVC3),
      
      .oFM_BMC_SAFS_SEL                     (wFM_BMC_SAFS_SEL),
      
      .oFM_SLPS4_CPU0_CPU_PLD_N             (wFM_SLPS4_CPU0_CPU_PLD_N),
      .oFM_SLPS3_CPU0_CPU_PLD_N             (wFM_SLPS3_CPU0_CPU_PLD_N),
      .oFM_SLPS4_CPU1_CPU_PLD_N             (wFM_SLPS4_CPU1_CPU_PLD_N),
      .oFM_SLPS3_CPU1_CPU_PLD_N             (wFM_SLPS3_CPU1_CPU_PLD_N),
      
      .oPWRGD_CPU0_LVC1_R                   (wPWRGD_CPU0_LVC1_R),
      .oMEM_PWR_FLT                         (wMEM_PWR_FLT),
      .oCPU_PWR_FLT                         (wCPU_PWR_FLT),

      .oPWRGD_PVNN_MAIN_CPU0_FF             (wPWRGD_PVNN_MAIN_CPU0_FF),
      .oPWRGD_PVNN_MAIN_CPU1_FF             (wPWRGD_PVNN_MAIN_CPU1_FF),

      .oHeartBeat                           (wPldHeartBeat),
      .oMasterCode                          (wMASTER_POST_CODE),
      .pwr_err_source                       (pwr_err_source),
      .pwr_restart                          (pwr_restart_sync),
      .force_to_enter_err                   (wForceToEnterErrSync2M),
      .force_to_enter_err_clear             (force_to_enter_err_clear),
      .pwr_restart_clear                    (pwr_restart_clear),
      .SMB_PCIE_STBY_LVC3_SCL               (SMB_PCIE_LVC3_SCL),
      .SMB_PCIE_STBY_LVC3_SDA               (SMB_PCIE_LVC3_SDA),
      .SMB_PEHPCPU0_LVC3_FPGA_SCL           (SMB_PEHPCPU0_LVC3_FPGA_SCL),
      .SMB_PEHPCPU0_LVC3_FPGA_SDA           (SMB_PEHPCPU0_LVC3_FPGA_SDA),
      .FM_FAULT_LED_AMBER_M2_EDSFF_N        (FM_CPU0_EDSFFX4_LED_LVC3),
      .FM_PWRDIS_EDSFF                      (FM_CPU0_EDSFFX4_PWRDIS_LVC3),

      .oCpu0IntrPrsnt_n                     (wCpu0IntrPrsnt_n),
      .oCpu1IntrPrsnt_n                     (wCpu1IntrPrsnt_n),
      .oCpu0IntrTypeABn                     (wCpu0IntrTypeABn),
      .oCpu1IntrTypeABn                     (wCpu1IntrTypeABn),

	  .iLegacyNode                          (wLegacyNodeSync2M),
	  .iwInModular                          (wInModular),
	  .iwInRP                               (wInRP),

      .iGLBRST_HOLD_OFF                     ( (wGlbRstHoldOffEnaSync2M && wGlbRstHoldOffSync2M) || wGlbRstHaltModeSync2M ),   // BMC or Jumper hold off Global Reset
	  .PWRGD_P1V2_MAX10_AUX_PLD_R_LVC3      (wPwrGdP1V2Max10AuxSync2M),

	  .RST_PLD_PCIE_CPU0_x16_PERST          (wRST_PLD_PCIE_CPU0_x16_PERST_LVC3_R_N  ),
      .RST_PLD_PCIE_CPU0_DCSCM_PERST        (wRST_PLD_PCIE_CPU0_DCSCM_PERST_LVC3_R_N),
      .RST_PLD_PCIE_CPU0_DEV_PERST_R_N      (wRST_PLD_PCIE_CPU0_DEV_PERST_LVC3_R_N  ),
      .RST_PLD_PCIE_CPU1_DEV_PERST_R_N      (wRST_PLD_PCIE_CPU1_DEV_PERST_LVC3_R_N  ),
	  .iClk_50M                             (wClk_50M),


      .CurrentTime_Masterfub                (),

      .rjo_ready                           (wRjoReadySync2M    ),
      .rjo_ready_sec                       (wRjoReadySecSync2M ),
	  
	  .oMBVR_ready_sync                    (wMBVR_ready_sync), // MBVR flow for Modular
	  .iMBVR_ready_ack                     (wMbvrReadyAckSync2M),  // MBVR flow for Modular
	  
	  .iCPU0_PWRBTN_FPGA_N                 (wFmCpu0PwrbtnFpgaSync2M_n),
	  .iCPU0_RSTBTN_FPGA_N                 (wFmRstCpu0RstBtnFpgaSync2M_n),
	  
	  .oFM_THERMTRIP_CPU0_LED_LATCHED      (oFM_THERMTRIP_CPU0_LED_LATCHED),
	  .oFM_THERMTRIP_CPU1_LED_LATCHED      (oFM_THERMTRIP_CPU1_LED_LATCHED)
	  
      );


// Synchronizer for Modular systems.
level_sync sync_inMod       (.clk(wClk_100M), .signal_in(wInModular                              ), .signal_sync(wInModular_sync100 )); 
level_sync sync_MBVR_ack    (.clk(wClk_100M), .signal_in(wMBVR_ready_ack                         ), .signal_sync(wMBVR_ready_ack_sync100 )); 
level_sync sync_PERST_B0    (.clk(wClk_100M), .signal_in(wFM_RST_PERST_BIT0_LVC25                ), .signal_sync(wFM_RST_PERST_BIT0_sync100 )); 
level_sync sync_PERST_B1    (.clk(wClk_100M), .signal_in(wFM_RST_PERST_BIT1_LVC25                ), .signal_sync(wFM_RST_PERST_BIT1_sync100 )); 
level_sync sync_PERST_B3    (.clk(wClk_100M), .signal_in(wFM_RST_PERST_BIT3_LVC25                ), .signal_sync(wFM_RST_PERST_BIT3_sync100 )); 
level_sync sync_PERST_CPU0  (.clk(wClk_100M), .signal_in(wRST_PLD_PCIE_CPU0_DEV_PERST_LVC3_R_N   ), .signal_sync(wRST_PLD_PCIE_CPU0_DEV_PERST_sync100 ));
level_sync sync_PERST_CPU1  (.clk(wClk_100M), .signal_in(wRST_PLD_PCIE_CPU1_DEV_PERST_LVC3_R_N   ), .signal_sync(wRST_PLD_PCIE_CPU1_DEV_PERST_sync100 )); 
level_sync sync_PERST_DCSCM (.clk(wClk_100M), .signal_in(wRST_PLD_PCIE_CPU0_DCSCM_PERST_LVC3_R_N ), .signal_sync(wRST_PLD_PCIE_CPU0_DCSCM_PERST_sync100 )); 

// 20ns delays for PERST in MBVR power down flow, This is to compensate the propagation time in Modular FPGA for CPUPWRGD
    delay #(.COUNT(T_20ns_100M)) 
        Timer20ns_cpu0(
            .iClk    ( wClk_100M                     ),
            .iRst    ( wRst_n                        ),
            .iStart  ( wInModular_sync100 && wMBVR_ready_ack_sync100 && !wFM_RST_PERST_BIT0_sync100 && !wRST_PLD_PCIE_CPU0_DEV_PERST_sync100 ), //If we are in Modular,(CPUPWRGD), and PERST is down
            .iClrCnt ( 1'b0                          ),
            .oDone   ( wDoneTimer_20ns_CPU0          )
        );
		
    delay #(.COUNT(T_20ns_100M)) 
        Timer20ns_cpu1(
            .iClk    ( wClk_100M                     ),
            .iRst    ( wRst_n                        ),
            .iStart  ( wInModular_sync100 && wMBVR_ready_ack_sync100 && !wFM_RST_PERST_BIT1_sync100 && !wRST_PLD_PCIE_CPU1_DEV_PERST_sync100 ), //If we are in Modular, (CPUPWRGD), and PERST is down
            .iClrCnt ( 1'b0                          ),
            .oDone   ( wDoneTimer_20ns_CPU1          )
        );

    delay #(.COUNT(T_20ns_100M)) 
        Timer20ns_dcscm(
            .iClk    ( wClk_100M                     ),
            .iRst    ( wRst_n                        ),
            .iStart  ( wInModular_sync100 && wMBVR_ready_ack_sync100 && !wFM_RST_PERST_BIT3_sync100 && !wRST_PLD_PCIE_CPU0_DCSCM_PERST_sync100 ), //If we are in Modular, (CPUPWRGD), and PERST is down
            .iClrCnt ( 1'b0                          ),
            .oDone   ( wDoneTimer_20ns_DCSCM         )
        );

   // PERST outputs for Modular MBVR Flow. If we are in Modular system and (CPUPWRGD) is selected, then the output is delayed 20 ns, else the outuput is the one that comes from master sequencer.
   assign RST_PLD_PCIE_CPU0_DEV_PERST_LVC3_R_N   = wInModular_sync100 && !wFM_RST_PERST_BIT0_sync100  && wMBVR_ready_ack_sync100  ? !wDoneTimer_20ns_CPU0  : wRST_PLD_PCIE_CPU0_DEV_PERST_sync100   ;
   assign RST_PLD_PCIE_CPU1_DEV_PERST_LVC3_R_N   = wInModular_sync100 && !wFM_RST_PERST_BIT1_sync100  && wMBVR_ready_ack_sync100  ? !wDoneTimer_20ns_CPU1  : wRST_PLD_PCIE_CPU1_DEV_PERST_sync100   ;
   assign RST_PLD_PCIE_CPU0_DCSCM_PERST_LVC3_R_N = wInModular_sync100 && !wFM_RST_PERST_BIT3_sync100  && wMBVR_ready_ack_sync100  ? !wDoneTimer_20ns_DCSCM : wRST_PLD_PCIE_CPU0_DCSCM_PERST_sync100 ;
   assign RST_PLD_PCIE_CPU0_x16_PERST_LVC3_R_N   = wInModular_sync100 && !wFM_RST_PERST_BIT0_sync100  && wMBVR_ready_ack_sync100  ? !wDoneTimer_20ns_CPU0  : wRST_PLD_PCIE_CPU0_DEV_PERST_sync100   ; 
   //--------------------------------------------------------------------------------------------------------------


   //Sample I2C values and synchronize into our domain
   always @( posedge wClk_20M )
     begin
        if(Reset)
          begin
             i2c_pfr_clk_sync   <= 1'b0;
             i2c_pfr_data_sync  <= 1'b0;
             i2c_pfr_clk_in     <= 1'b0;
             i2c_pfr_data_in    <= 1'b0;
          end
        else
          begin
             i2c_pfr_clk_sync  <= SMB_CPLD_UPDATE_STBY_LVC3_SCL;
             i2c_pfr_data_sync <= SMB_CPLD_UPDATE_STBY_LVC3_SDA;
             i2c_pfr_clk_in    <= i2c_pfr_clk_sync;
             i2c_pfr_data_in   <= i2c_pfr_data_sync;
          end // else: !if(!wRst_20M_n)
     end // always @ ( posedge wClk_20M, negedge wRst_20M_n )
   
   //This i2c_slave is connected to PFR

   i2c_slv i2c_slv_main_pfr
     (
      .Clock                     (   wClk_20M                                 ),
      .Reset                     (   Reset                                ),
      .SclIn                     (   i2c_pfr_clk_in                           ),
      .SdaIn                     (   i2c_pfr_data_in                          ),
      .SdaOut                    (   i2c_pfr_data_oe                          ),
      .DeviceAddress             (   8'h5C                                    ),
      //avmm_intf
      .avmm_address              (   avmm_pfr_address                         ),
      .avmm_writedata            (   avmm_pfr_writedata                       ),
      .avmm_write                (   avmm_pfr_write                           ),
      .avmm_read                 (   avmm_pfr_read                            ),
      .avmm_readvalid            (   avmm_pfr_readvalid                       ),
      .avmm_readdata             (   avmm_pfr_readdata                        ),
      .I2C_CRC_Error             (   I2C_CRC_Error                            )
      );


   assign SMB_CPLD_UPDATE_STBY_LVC3_SDA = i2c_pfr_data_oe ? 1'bZ : 1'b0;


   avmm_mux_1to2
     #(
       .SLV1_ADDR_LOW             (   32'h0000                                 ),
       .SLV1_ADDR_High            (   32'h1FFF                                 ),
       .SLV2_ADDR_LOW             (   32'h2100                                 ),
       .SLV2_ADDR_High            (   32'h21FF                                 )
       )
   avmm_mux_main_1to2_inst
     (
      .clk                        (   wClk_20M                                 ),
      .rst_n                      (   Reset_N                                 ),
      //AVMM_Single_Master, connected to I2C slave AVMM
      .mst_address                ({  16'b0, avmm_pfr_address                 }),
      .mst_write                  (   avmm_pfr_write                           ),
      .mst_writedata              ({  16'b0, avmm_pfr_writedata               }),
      .mst_read                   (   avmm_pfr_read                            ),
      .mst_readdata               ({  avmm_pfr_readdata_h, avmm_pfr_readdata  }),
      .mst_readdatavalid          (   avmm_pfr_readvalid                       ),
      .mst_waitrequest            (                                            ),
      .mst_byteenable             (   4'b1111                                  ),
      //AVMM_Slave_1, connect to rsu
      .slv1_address               (   avmm_rsu_address                         ),
      .slv1_write                 (   avmm_rsu_write                           ),
      .slv1_writedata             (   avmm_rsu_writedata                       ),
      .slv1_read                  (   avmm_rsu_read                            ),
      .slv1_readdata              (   avmm_rsu_readdata                        ),
      .slv1_readdatavalid         (   avmm_rsu_readdatavalid                   ),
      .slv1_waitrequest           (   1'b0                                     ),
      .slv1_byteenable            (                                            ),
      //AVMM_Slave_2, connect to scm pfr CSR
      .slv2_address               (   main_pfr_csr_address                     ),
      .slv2_write                 (   main_pfr_csr_write                       ),
      .slv2_writedata             (   main_pfr_csr_writedata                   ),
      .slv2_read                  (   main_pfr_csr_read                        ),
      .slv2_readdata              (   main_pfr_csr_readdata                    ),
      .slv2_readdatavalid         (   main_pfr_csr_readdatavalid               ),
      .slv2_waitrequest           (   main_pfr_csr_waitrequest                 ),
      .slv2_byteenable            (   main_pfr_csr_byteenable                  )
      );
wire T_Reset;

    //Store SCM PFR CSR for PFR CPLD to access

      cpu_pfr_csr main_pfr_csr_inst
      (
       .clk                      (     wClk_20M                                 ),
       .reset                    (     Reset                                    ),
       //avmm interface
       .avmm_address             (     main_pfr_csr_address                     ),
       .avmm_write               (     main_pfr_csr_write                       ),
       .avmm_writedata           (     main_pfr_csr_writedata                   ),
       .avmm_read                (     main_pfr_csr_read                        ),
       .avmm_readdata            (     main_pfr_csr_readdata                    ),
       .avmm_readdatavalid       (     main_pfr_csr_readdatavalid               ),
       .avmm_waitrequest         (     main_pfr_csr_waitrequest                 ),
       .avmm_byteenable          (     main_pfr_csr_byteenable                  ),
       .T_Reset                  (     T_Reset                                  )
       );

   GlitchFilter2 #(.NUMBER_OF_SIGNALS(2), .RST_VALUE(2'b10))
   rsu_filter
     (
      .iClk(wClk_20M),
      .iARst_n(Reset_N),
      .iSRst_n(1'b1),
      .iEna(1'b1),
      .iSignal({wCPLD_RSU_HIDE,
                FM_CPU0_GLB_RST_WARN_FPGA_LVC18_N_R
	      }),
      .oFilteredSignals({wCPLD_RSU_HIDE_sync,

                         FM_CPU0_GLB_RST_WARN_PLD_N_FF
		       })
      );





    //Remote System Update
   RSU_WRAPPER
     #(
       .FwRevision             ( 16'h10CF                      ),
       .DeviceAddr             ( 8'h5C                         ),
       .DeviceType             ( 16'h11AD                      ),
       .SupportMode            ( 8'h06                         )
       )
   rsu_inst
     (
      .Clock                   ( wClk_20M                      ),
      .PllLocked               ( wDRst_n                        ),
      .RSU_Hide                ( wCPLD_RSU_HIDE_sync           ),
      .Reset_N                 ( Reset_N                      ), //output, delayed version of pll_locked
      .LockPin                 ( 1'b0                          ),//don't use lock
      .I2C_CRC_Error           ( I2C_CRC_Error                 ), 
      //i2C slave avmm intf
      .avmm_address            ( avmm_rsu_address[15:0]        ),
      .avmm_writedata          ( avmm_rsu_writedata[15:0]      ),
      .avmm_write              ( avmm_rsu_write                ),
      .avmm_read               ( avmm_rsu_read                 ),
      .avmm_readvalid          ( avmm_rsu_readdatavalid        ),
      .avmm_readdata           ( avmm_rsu_readdata[15:0]       ),
      //flash avmm intf
      .avmm_csr_addr           ( RSU_flash_csr_addr            ),
      .avmm_csr_read           ( RSU_flash_csr_read            ),
      .avmm_csr_writedata      ( RSU_flash_csr_writedata       ),
      .avmm_csr_write          ( RSU_flash_csr_write           ),
      .avmm_csr_readdata       ( RSU_flash_csr_readdata        ),
      .avmm_data_addr          ( RSU_flash_data_addr           ),
      .avmm_data_read          ( RSU_flash_data_read           ),
      .avmm_data_writedata     ( RSU_flash_data_writedata      ),
      .avmm_data_write         ( RSU_flash_data_write          ),
      .avmm_data_readdata      ( RSU_flash_data_readdata       ),
      .avmm_data_waitrequest   ( RSU_flash_data_waitrequest    ),
      .avmm_data_readdatavalid ( RSU_flash_data_readdatavalid  ),
      .avmm_data_burstcount    ( RSU_flash_data_burstcount     )
      );

assign Reset = ~Reset_N;

   //Instantiate Internal Flash

// This module is the  memory flash ip, used for for RJO and RJU.
//The configuration is double compressed.
      cpu_flash main_flash_inst
     (
      .clock                    (       wClk_20M                        ),
      .reset_n                  (       Reset_N                         ),
      .avmm_csr_addr            (       flash_csr_addr                  ),
      .avmm_csr_read            (       flash_csr_read                  ),
      .avmm_csr_writedata       (       flash_csr_writedata             ),
      .avmm_csr_write           (       flash_csr_write                 ),
      .avmm_csr_readdata        (       flash_csr_readdata              ),
      .avmm_data_addr           (       flash_data_addr [16:0]          ),
      .avmm_data_read           (       flash_data_read                 ),
      .avmm_data_writedata      (       flash_data_writedata            ),
      .avmm_data_write          (       flash_data_write                ),
      .avmm_data_readdata       (       flash_data_readdata             ),
      .avmm_data_waitrequest    (       flash_data_waitrequest          ),
      .avmm_data_readdatavalid  (       flash_data_readdatavalid        ),
      .avmm_data_burstcount     (       flash_data_burstcount           )
      );

   
   
   assign uart_rxd[0]             = PWRGD_CPU0_PLT_AUX_PWRGD_FPGA_LVC18_R ? UART_CPU0_TXD_LVC18_R3 : 1'b0;
   assign uart_cts[0]             = PWRGD_CPU0_PLT_AUX_PWRGD_FPGA_LVC18_R ? UART_CPU0_RTS_LVC18_R3 : 1'b0;


   assign UART_CPU1_RXD_LVC18_R3  = PWRGD_CPU1_PLT_AUX_PWRGD_FPGA_LVC18 ? uart_txd[1] : 1'b0;
   assign UART_CPU1_CTS_LVC18_R3  = PWRGD_CPU1_PLT_AUX_PWRGD_FPGA_LVC18 ? uart_rts[1] : 1'b0;
   assign uart_rxd[1]             = PWRGD_CPU1_PLT_AUX_PWRGD_FPGA_LVC18 ? UART_CPU1_TXD_LVC18_R3 : 1'b0;
   assign uart_cts[1]             = PWRGD_CPU1_PLT_AUX_PWRGD_FPGA_LVC18 ? UART_CPU1_RTS_LVC18_R3 : 1'b0;



   assign RST_CPU0_RTCRST_PLD_R_N = wRST_CPU0_RTCRST_N ? 1'b0 : 1'bZ;

   //IOC LVDS Module, Slave at CPU_FPGA Side
   ioc_top
     #(
       .MASTER               ( 0  ),
       .BUS_SPEED_KHZ        ( 400),
       .NORMAL_GPIO_RST_VALUE( {40'b0,         /*GPIO_RSVD*/
                                8'b0000_0000,  /*GPIO_VALUE_71_64*/
                                8'b0000_0000,  /*GPIO_VALUE_63_56*/
                                8'b0000_0000,  /*GPIO_VALUE_55_48*/
                                8'b0110_0011,  /*GPIO_VALUE_47_40*/
                                8'b0111_0001,  /*GPIO_VALUE_39_32*/
                                8'b0000_0000,  /*GPIO_VALUE_31_24*/
                                8'b0000_0000,  /*GPIO_VALUE_23_16*/
                                8'b0000_0000,  /*GPIO_VALUE_15_8*/
                                8'b0000_0000   /*GPIO_VALUE_7_0*/
                                })
       )
   cpu_ioc
     (
      .clk                ( wClk_20M                      ),
      .rst_n              ( Reset_N                      ),
      .tx_coreclock       ( wTxCoreClk                    ), //tx_lvds internal pll clock output
      .tx_pll_locked      ( wTxPllLock                    ), //tx_lvds internal pll lock output
      .aligned            ( wMcsiAligned                  ),
      //LVDS link
      .lvds_clk_in        ( LVDS_LVC25_CLK_RX_DP          ),
      .lvds_clk_out       ( LVDS_LVC25_CLK_TX_DP          ),
      .lvds_rx_in         ( LVDS_LVC25_RX_DP              ),
      .lvds_tx_out        ( LVDS_LVC25_TX_DP              ),
      //SMBus
      .smb_scl            ( {wSclRsvd[6:0],
                             SMB_PIROM_SCL,
                             SMB_PMBUS1_LVC3_SCL,
                             SMB_THERMAL_SENSOR_LVC3_SCL,
                             SMB_PMBUS2_LVC3_SCL,
                             SMB_CHASSIS_SENSOR_LVC3_SCL} ),
      .smb_sda            ( {wSdaRsvd[6:0],
                             SMB_PIROM_SDA,
                             SMB_PMBUS1_LVC3_SDA,
                             SMB_THERMAL_SENSOR_LVC3_SDA,
                             SMB_PMBUS2_LVC3_SDA,
                             SMB_CHASSIS_SENSOR_LVC3_SDA} ),
      //gpio_in
      .gpio_in            ( wLvdsGpioIn                   ),
      //gpio_out
      .gpio_out           ( wLvdsGpioOut                  ),
      //UART over LVDS
      .uart_rxd           ( uart_rxd                      ),
      .uart_cts           ( uart_cts                      ),
      .uart_txd           ( uart_txd                      ), //output
      .uart_rts           ( uart_rts                      ), //output
      //AVMM slave only exist on ioc_master side
      .avmm_slv_addr      ( 'b0                           ),
      .avmm_slv_read      ( 'b0                           ),
      .avmm_slv_write     ( 'b0                           ),
      .avmm_slv_wdata     ( 'b0                           ),
      .avmm_slv_byteen    ( 'b0                           ),
      .avmm_slv_rdata     (                               ),
      .avmm_slv_rdvalid   (                               ),
      .avmm_slv_waitrq    (                               ),
      //AVMM master only exist on ioc_slave side
      .avmm_mst_addr      ( avmm_mst_addr                 ),
      .avmm_mst_read      ( avmm_mst_read                 ),
      .avmm_mst_write     ( avmm_mst_write                ),
      .avmm_mst_wdata     ( avmm_mst_wdata                ),
      .avmm_mst_byteen    ( avmm_mst_byteen               ),
      .avmm_mst_rdata     ( avmm_mst_rdata                ),
      .avmm_mst_rdvalid   ( avmm_mst_rdvalid              ),
      .avmm_mst_waitrq    ( avmm_mst_waitrq               ),
      //AVMM_master
      .avmm_csr_addr      ( mcsi_csr_address[15:0]        ),
      .avmm_csr_read      ( mcsi_csr_read                 ),
      .avmm_csr_write     ( mcsi_csr_write                ),
      .avmm_csr_wdata     ( mcsi_csr_writedata            ),
      .avmm_csr_rdata     ( mcsi_csr_readdata             ),
      .avmm_csr_byteen    ( mcsi_csr_byteenable           ),
      .avmm_csr_rdvalid   ( mcsi_csr_readdatavalid        )

      );


   //LVDS GPIO_IN (Main PLD to BMC SGPIO data over LVDS I/F, passing thru SCM PLD)

   assign wRstBmcSrstDio_n = 1'b1;  //for BNC-RP always HIGH


   assign wLvdsGpioIn = {
                         17'b0,
						 
						 wFmHpfrInSyncLvds, // output to PFR  from Modular FPGA through LVDS.
						 wLegacyNodeSync2M,// output to PFR  from Modular FPGA through LVDS.
						 wFmHpfrActive,     // HPFR Enable (std_alone) output to PFR  from Modular FPGA through LVDS.

                         //GPIO in 91:88
                         1'b0, //wSMRJODone,
                         wPwrGdCpu0S0PwrOkSyncLvds,//1'b0,
                         1'b0,                                  
                         1'b0,                                  

                         //GPIO in 87:80
                         1'b0,                                  
						 wFmTtkSpiEnRjc_nSyncLvds,       //added this signal from RJO
                         wFmPfrDebugJumperRjc_nSyncLvds, //added this signal from RJO
                         wPfrForceRecoveryRjc_nSynLvds,  //added this signal from RJO

                         wCpuMismatchSyncLvds,
                         wMemPwrFltSyncLvds,
                         wCpuPwrFltSyncLvds,
                         wPsuFaultSyncLvds,
                         //GPIO in 79:72
                         wP3V3FaultSyncLvds,
                         wCpuAuxPwrFltSyncLvds,
                         wFM_DUAL_PARTITION_LVC3_N,
                         wFM_PARTITION_SEL_LVC3,
                         wValDbgJumperEnSyncLvds_n,
                         wBiosImageSwapSyncLvds_n,
                         FM_BOARD_SKU_ID5,
                         wRstCpu0PltrstSync_FF,
                         //GPIO in 71:64
                         wRstCpu1PltrstSync_FF,
                         wFM_CPU0_GPIO4_EAF_BMC_SAFS_SEL_LVC1_LATCHED,
                         wPWRGD_PS_PWROK_CPU_PLD_R,
                         wSlpS4Cpu0SyncLvds_n,
                         wSlpS3Cpu0SyncLvds_n,
                         wPwrGdCpu0SyncLvds,
                         wSlpS4Cpu1SyncLvds_n,
                         wSlpS3Cpu1SyncLvds_n,
                         //GPIO in 63:56
                         wFM_CPU0_PKGID0,
                         wFM_CPU0_PKGID1,
                         wFM_CPU0_PKGID2,
                         FM_CPU0_PROC_ID0,
                         FM_CPU0_PROC_ID1,
                         wFmCpu0sktoccPld_nSyncLvds,
                         wFM_CPU1_PKGID0,
                         wFM_CPU1_PKGID1,
                         //GPIO in 55:48
                         wFM_CPU1_PKGID2,
                         FM_CPU1_PROC_ID0,
                         FM_CPU1_PROC_ID1,
                         wFmCpu1sktoccPld_nSyncLvds,
                         wFpPwrBtn_n_FF,
                         wFpRstBtn_n_FF,
                         wFpIdBtn_n_FF,
                         wFpNmiBtn_n_FF,
                         //GPIO in 47:40
                         wFM_SERIAL_BOOT,
                         wFmSmbBmcNvmeAlert_n_FF,
                         wRstBmcSrstDio_n,
                         FM_BOARD_SKU_ID0,   //for Modular Testing
                         FM_BOARD_SKU_ID1,
                         FM_BOARD_SKU_ID2,   //for Modular Testing
                         FM_BOARD_SKU_ID3,
                         FM_BOARD_SKU_ID4,
                         //GPIO in 39:32
                         FM_BOARD_REV_ID0,
                         FM_BOARD_REV_ID1,
                         FM_BOARD_REV_ID2,
                         wFM_STANDALONE_MODE_N,
                         wFM_4S_8S_MODE_N,
                         wFM_NODE_ID0,
                         wFM_NODE_ID1,
                         w1200VaOCSyncLvds,
                         //GPIO in 31:24
                         wIrqSml1PmbusAlert_n_FF,
                         wIrqCpu0VrHot_n_FF,
                         wIrqCpu1VrHot_n_FF,
                         wIrqCpu0MemVrHot_n_FF,
                         wIrqCpu1MemVrHot_n_FF,
                         wS3MCpu0CpldCrcError_FF,
                         wS3MCpu1CpldCrcError_FF,
                         wDbpPodPrsnt_n_FF,
                         //GPIO in 23:16
                         wCpu0CatErrEncodeSyncLvds[0],
                         wCpu0CatErrEncodeSyncLvds[1],
                         wCpu0RmcaEncodeSyncLvds[0],
                         wCpu0RmcaEncodeSyncLvds[1],
                         wCpu1CatErrEncodeSyncLvds[0],
                         wCpu1CatErrEncodeSyncLvds[1],
                         wCpu1RmcaEncodeSyncLvds[0],
                         wCpu1RmcaEncodeSyncLvds[1],
                         //GPIO in 15:8
                         wASDEnDet,
                         wCpu0ThermtripSyncLvds_n,
                         wCpu0MemtripSyncLvds_n,
                         wCpu0MemHotOut_n_FF,
                         wCpu0Err0_n_FF,
                         wCpu0Err1_n_FF,
                         wCpu0Err2_n_FF,
                         wCpu0MonFail_n_FF,
                         //GPIO in 7:0
                         wCpu1ThermtripSyncLvds_n,
                         wCpu1Memtrip_n_FF,
                         wCpu1MemHotOut_n_FF,
                         wCpu1Err0_n_FF,
                         wCpu1Err1_n_FF,
                         wCpu1Err2_n_FF,
                         wCpu1MonFail_n_FF,
                         wCpu1AuxPwrOkSyncLvds//wSCM_BMC_EN
                         };

   //from LvdsGpioOut to the corresponding signal

   assign wFM_HPFR_OUT                   =  wLvdsGpioOut[112];      // from PFR to   Modular FPGA through LVDS.

   assign wIRQ_BMC_CPU_NMI_P0            =  wLvdsGpioOut[111];
   assign wCPLD_RSU_HIDE                 =  wLvdsGpioOut[94];
   assign wSCMFPGAREV                    =  wLvdsGpioOut[93:86];
   assign wSCMFPGATEST                   =  wLvdsGpioOut[85:78];
   assign FM_TTK_SPI_EN_RJC_N_IN         =  wLvdsGpioOut[77];     //default value 1'b0,
   assign PFR_DEBUG_JUMPER_RJC_N_IN      =  wLvdsGpioOut[76];     //default value 1'b0,
   assign PFR_FORCE_RECOVERY_RJC_N_IN    =  wLvdsGpioOut[75];     //default value 1'b1,
   assign wFM_BMC_INIT_DONE              =  wLvdsGpioOut[74];     //default value 1'b0
   assign wFM_GLOBAL_RESET               =  wLvdsGpioOut[73];

   assign wCpu1IntrClkConfDone           = wLvdsGpioOut[72];


   assign wLED_CPU0_DIMM_CH1_8_FLT       =  wLvdsGpioOut[71:64]; //default value 1'b0,   to Secondary PLD thru SGPIO I/F
   assign wLED_CPU1_DIMM_CH1_8_FLT       =  wLvdsGpioOut[63:56]; //default value 1'b0,   to Secondary PLD thru SGPIO I/F
   ////GPIO out 47:40
   assign wSURPRISE_RESET                =  wLvdsGpioOut[47] ;   //default value 1'b0
   assign H_CPU0_BMC_TRUSTED_LVC1_N      =  wPWRGD_PVNN_MAIN_CPU0_FF ? wLvdsGpioOut[46] : 1'bZ;   //default value 1'b1    Directly out to board
   assign wRST_CPU0_RSTBTN_FPGA_LVC18_R_N =  PWRGD_CPU0_PLT_AUX_PWRGD_FPGA_LVC18_R ? wLvdsGpioOut[45] : 1'bZ;   //default value 1'b1,   Directly out to board
   assign wRST_CPU1_RTCRST_N             =  wLvdsGpioOut[44] ;   //default value 1'b0,   Directly out to board
   assign wRST_BMC_PCIE_MUX_R_N          =  wLvdsGpioOut[43] ;   //default value 1'b0,   Directly out to board
   assign wRST_BMC_HSBP_MUX_N            =  wLvdsGpioOut[42] ;   //default value 1'b0,   Directly out to board
   assign wFM_BMC_ONCTL_LVDS_N                =  wLvdsGpioOut[41] ;   //default value 1'b1,   To be used by internal logic ONLY
   assign wFM_CPU0_PWRBTN_FPGA_R_LVC18_N  =  PWRGD_CPU0_PLT_AUX_PWRGD_FPGA_LVC18_R ? wLvdsGpioOut[40] : 1'bZ;   //default value 1'b1,   Directly out to board
   //GPIO out 39:32
   assign wFM_BMC_BMCINIT                =  wLvdsGpioOut[39] ;   //default value 1'b0,   used by internal logic to produce outputs for both CPUs according to INITDISABLE and Partition logic
   assign FP_ID_LED_N                    =  wLvdsGpioOut[38] ;   //default value 1'b1,   Directly out to board
   assign FP_LED_STATUS_AMBER_N          =  wLvdsGpioOut[37] ;   //default value 1'b1,   Directly out to board
   assign FP_LED_STATUS_GREEN_N          =  wLvdsGpioOut[36] ;   //default value 1'b1,   Directly out to board
   assign SPEAKER_BMC_R                 =  wLvdsGpioOut[35] ;  //default value 1'b0,   to Secondary PLD thru SGPIO I/F
   assign wFM_SKT0_FAULT_LED             =  wLvdsGpioOut[34] ;   //default value 1'b0,  to Secondary PLD thru SGPIO I/F
   assign wFM_SKT1_FAULT_LED             =  wLvdsGpioOut[33] ;   //default value 1'b0,   Directly out to board
   assign FM_BMC_CPU_FBRK_OUT_LVC3_N     =  wLvdsGpioOut[32] ;   //default value 1'b1,   Directly out to board
   //GPIO out 31:24
   assign FM_SPD_SWITCH_CTRL_LVC3_N      =  wLvdsGpioOut[31] ;   //default value 1'b0,   Directly out to board
   assign wFM_TPM_EN_PULSE               =  wLvdsGpioOut[30] ;   //default value 1'b0,   used by internal logic to produce TPM PLTRST outputs for each SKT
   assign wRST_CPU0_RTCRST_N             =  wLvdsGpioOut[27] ;   //default value 1'b0,   Directly out to board
   assign wSCM_BMC_AUX_PWR_OK            =  wLvdsGpioOut[26] ;   //default value 1'b0;   To be used by internal logic
   assign wSCM_BMC_AUX_PWR_FAULT         =  wLvdsGpioOut[25] ;   //default value 1'b0;   To be used by internal logic
   assign wSCM_PWR_FAULT                 =  wLvdsGpioOut[24] ;   //default value 1'b0;   to Secondary PLD thru SGPIO I/F
   //GPIO out 23:16
   assign wBMC_PWR_FAULT                 =  wLvdsGpioOut[23] ;   //default value 1'b0;   to Secondary PLD thru SGPIO I/F
   assign wP5V_MAIN_PWR_FAULT            =  wLvdsGpioOut[22] ;   //default value 1'b0;   to Secondary PLD thru SGPIO I/F
   assign wRST_PLTRST_CPU0_PLD_LVC18_N   =  wLvdsGpioOut[21] ;   //default value 1'b0,   Directly out to board and used by internal logic, and to DBG FPGA thru sGPIO
   assign RST_PLTRST_CPU1_PLD_R_LVC1_N   =  wInModular ? 1'bZ : wLvdsGpioOut[20] ;   //default value 1'b0,   Directly out to board and used by internal logic
   assign wAUX_PWRGD_CPU0_SCM            =  wLvdsGpioOut[19] ;   //default value 1'b0;   To be used by internal logic ONLY
   assign wAUX_PWRGD_CPU1_SCM            =  wLvdsGpioOut[18] ;   //default value 1'b0;   To be used by internal logic ONLY
   assign wFM_CK440Q_SSC0_R_LVC3         =  wLvdsGpioOut[17] ;   //default value 1'b0,   Directly out to board
   assign wFM_CK440Q_SSC1_R_LVC3         =  wLvdsGpioOut[16] ;   //default value 1'b0,   Directly out to board
   //GPIO out 15:8
   assign wBIOS_POST_CODE_LED_0          =  wLvdsGpioOut[15] ;   //default value 1'b0,   to Secondary PLD thru SGPIO I/F
   assign wBIOS_POST_CODE_LED_1          =  wLvdsGpioOut[14] ;   //default value 1'b0;
   assign wBIOS_POST_CODE_LED_2          =  wLvdsGpioOut[13] ;   //default value 1'b0;
   assign wBIOS_POST_CODE_LED_3          =  wLvdsGpioOut[12] ;   //default value 1'b0;
   assign wBIOS_POST_CODE_LED_4          =  wLvdsGpioOut[11] ;   //default value 1'b0;
   assign wBIOS_POST_CODE_LED_5          =  wLvdsGpioOut[10] ;   //default value 1'b0;
   assign wBIOS_POST_CODE_LED_6          =  wLvdsGpioOut[9]  ;   //default value 1'b0;
   assign wBIOS_POST_CODE_LED_7          =  wLvdsGpioOut[8]  ;   //default value 1'b0;
   //GPIO out 7:0
   assign wPFR_POST_CODE_LED_0           =  wLvdsGpioOut[7]  ;   //default value 1'b0,   to Secondary PLD thru SGPIO I/F
   assign wPFR_POST_CODE_LED_1           =  wLvdsGpioOut[6]  ;   //default value 1'b0;
   assign wPFR_POST_CODE_LED_2           =  wLvdsGpioOut[5]  ;   //default value 1'b0;
   assign wPFR_POST_CODE_LED_3           =  wLvdsGpioOut[4]  ;   //default value 1'b0;
   assign wPFR_POST_CODE_LED_4           =  wLvdsGpioOut[3]  ;   //default value 1'b0;
   assign wPFR_POST_CODE_LED_5           =  wLvdsGpioOut[2]  ;   //default value 1'b0;
   assign wPFR_POST_CODE_LED_6           =  wLvdsGpioOut[1]  ;   //default value 1'b0;
   assign wPFR_POST_CODE_LED_7           =  wLvdsGpioOut[0]  ;   //default value 1'b0;


   //this is for SSC signals, to only allow DC-SCM to drive them IF RJO is enabled in board
   assign FM_CK440Q_SSC0_R_LVC3 = wVAL_DBG_JUMPER_EN_N ? 1'bZ : wFM_CK440Q_SSC0_R_LVC3;
   assign FM_CK440Q_SSC1_R_LVC3 = wVAL_DBG_JUMPER_EN_N ? 1'bZ : wFM_CK440Q_SSC1_R_LVC3;
  
reg rSAFS_SEL, counter;
wire wFM_CPU0_GPIO4_EAF_BMC_SAFS_SEL_LVC1_LATCHED, wFM_CPU0_GPIO4_EAF_BMC_SAFS_SEL_LVC1_RJO;
wire gpio4_eaf_bmc_safs_sel_sync;

level_sync sync_safs (.clk(wClk_2M), .signal_in(wFM_CPU0_GPIO4_EAF_BMC_SAFS_SEL_LVC1_RJO ), .signal_sync(gpio4_eaf_bmc_safs_sel_sync ));   

   	//This logic is to latch the value of SAFS_SEL with AUX_PWRGD assertion
	always @ (posedge wClk_2M or negedge wRst_n) begin
        if (!wRst_n) begin
		   rSAFS_SEL    <= 1'b0;
		   counter    <= 1'b0;
        end	
	    else if ( (wPWRGD_PVNN_MAIN_CPU0_FF && FM_PVNN_AUX_CPU0_EN_R_LVC25) && counter == 1'b0) begin
				rSAFS_SEL    <= gpio4_eaf_bmc_safs_sel_sync;
				counter      <= 1'b1;
			    end 
		end //always
	assign wFM_CPU0_GPIO4_EAF_BMC_SAFS_SEL_LVC1_LATCHED         = rSAFS_SEL;

	
	assign FM_CPU0_GPIO4_EAF_BMC_SAFS_SEL_LVC1 = !wOvEnable_n [25] ? wFM_CPU0_GPIO4_EAF_BMC_SAFS_SEL_LVC1_RJO : 1'bZ;

   //-------------------------------------------------------------------------------------------------------------------------------------------------------------
   //SGPIO Main2Modular  (slave instance as Secondary/Modular PLD is the master)

   localparam SGPIO_MAIN2MOD = 20;


   always @(*)
     begin
        wCpu1BiosPostCmplt_n = 1'b1;
        if ({wBIOS_POST_CODE_LED_7,wBIOS_POST_CODE_LED_6,wBIOS_POST_CODE_LED_5,wBIOS_POST_CODE_LED_4,wBIOS_POST_CODE_LED_3,wBIOS_POST_CODE_LED_2,wBIOS_POST_CODE_LED_1,wBIOS_POST_CODE_LED_0} == 8'h57)
          wCpu0BiosPostCmplt_n <= 1'b0;
        else
          wCpu0BiosPostCmplt_n <= 1'b1;
     end

`ifdef SECONDARY_FPGA

   ngsx #(.BYTE_REGS(SGPIO_MAIN2MOD), .RST_VALUE_RX(160'hFF_FF_FF_FF_FF_FF_FF_FF_FF_FF_FF_FF_FF_FF_FF_F9_FF_04_80__07), .RST_VALUE_TX(160'h00_01_00_03_00_00_00_00_00_00_00_FF_00_70_00_00_00_00_00_45))
   SgpioMain2ModPlds(                                                                                                 
                     .iRst_n(wRst_n),                     //active low reset signal (driven from internal FPGA logic)
                     .iClk_2M(wClk_2M),                   //2M clock from internal logic to run rst condition timer
                     .iMClk(SGPIO_MAIN_MOD_FPGA_CLK_LVC18),     //serial clock (driven from SGPIO master)
                     .iLoad_n(SGPIO_MAIN_MOD_FPGA_LD_LVC18_N),  //Load signal (driven from SGPIO master to capture serial data input in parallel register)
                     .iSData(SGPIO_MAIN_MOD_FPGA_DOUT_LVC18),   //Serial data input (driven from SGPIO master)
                     .iPData                              //Parallel data from internal logic to master
                     ({

                       4'h00,                                                    //byte 19      //            159:156

                       rFmHpmStbyRdy_SyncSGPIO,                                 //        bit 155 HPM_STBY_RDY to sync in Modular platform

                       FM_CPU0_EDSFFX4_EXPCARD_IO0_LVC3_R,                      // bit 154 bifurcation FM_CPU0_EDSFFX4_EXPCARD_IO0_LVC3_R
                       FM_CPU1_RIGHT_RISER_WIDTH_LVC18,                         // bit 153  bifurcation -
                       FM_CPU1_RIGHT_RISER_MODE_LVC18_N,                        // bit 152
                       FM_CPU0_LEFT_RISER_WIDTH_LVC18,                          // bit 151
                       FM_CPU0_LEFT_RISER_MODE_LVC18_N,                         // bit 150
					   1'b0,                                                    // bit 149                    
					   FM_BOARD_REV_ID2,                                        //		  bit 148 Fjplasce oct/25/22: To fix the hook 3 Issue in Modular
					   FM_BOARD_REV_ID1,                                        //		  bit 147 Fjplasce oct/25/22: To fix the hook 3 Issue in Modular
					   FM_BOARD_REV_ID0,                                        //		  bit 146 Fjplasce oct/25/22: To fix the hook 3 Issue in Modular

                       rRstPltrstCpu1PldR_n_SyncSGPIO,                          //        bit 145
                       rRstCpu0_n_SyncSGPIO,                                    //         bit 144 to control Partition_ID in Secondary FPGA
	                   rFmDualPartitionQs_n_SyncSGPIO,                          //  byte 17        bit 143
                       rFmAsdEnDet_SyncSGPIO,                                   //        bit 142
                       rPwrgdPvnnMainCpu1_SyncSGPIO,                            //        bit 141
                       rPwrgdPvnnMainCpu0_SyncSGPIO,                            //        bit 140
                       PWRGD_P1V0_AUX,                                          //        bit 139
                       wSMPldUpgradeSync,                                       //        bit 138
                       rPwrgdCpu1Fpga_SyncSGPIO,                                //        bit 137
                       rPwrgdCpu0S0PwrokR_SyncSGPIO,                            //        bit 136

                       wPfrLocalSync,                                           //byte 16 bit 135
                       wFM_SKT1_FAULT_LED,                                      //        bit 134

		               wFM_SKT0_FAULT_LED_SECFPGA,			                    //         bit 133   //Implementation for Global Reset Halt Mode

                       1'b0,                                 //        bit 132 
                       rFmThermtripCpu1LedLatched_SyncSGPIO,                    //        bit 131   
					   rFmThermtripCpu0LedLatched_SyncSGPIO,                    //        bit 130   
                       rHCpu1CaterrR2_n_SyncSGPIO,                              //        bit 129
                       rHCpu0CaterrR2_n_SyncSGPIO,                              //        bit 128
                       wLED_CPU1_DIMM_CH1_8_FLT,                                 //byte 15
                       wLED_CPU0_DIMM_CH1_8_FLT,                                 //byte 14
                       wCPU1_FLT_CODE,                                           //byte 13
                       wCPU0_FLT_CODE,                                           //byte 12
                       2'b00,                                                    //byte 11 bits 95:94
                       wCPU1_DIMM_FLT_CODE,                                      //        bits 93:88
                       rMbvrReadySync_SyncSGPIO,                                 //byte 10 bit 87 MBVR flow for Modular
					   rPwrgdCpu0PltAuxPwrgdFpga_SyncSGPIO,                      //		   bit 86 
                       wCPU0_DIMM_FLT_CODE,                                      //        bits 85:80
                       wPFR_POST_CODE_LED_7,                                     //byte 9
                       wPFR_POST_CODE_LED_6,
                       wPFR_POST_CODE_LED_5,
                       wPFR_POST_CODE_LED_4,
                       wPFR_POST_CODE_LED_3,
                       wPFR_POST_CODE_LED_2,
                       wPFR_POST_CODE_LED_1,
                       wPFR_POST_CODE_LED_0,
                       wBIOS_POST_CODE_LED_7,                                     //byte 8
                       wBIOS_POST_CODE_LED_6,
                       wBIOS_POST_CODE_LED_5,
                       wBIOS_POST_CODE_LED_4,
                       wBIOS_POST_CODE_LED_3,
                       wBIOS_POST_CODE_LED_2,
                       wBIOS_POST_CODE_LED_1,
                       wBIOS_POST_CODE_LED_0,
                       wP5V_MAIN_PWR_FAULT,                                       //byte 7  bit 63
                       wPSU_FLT_CODE,                                             //        bits 62:60
                       wMASTER_POST_CODE,                                         //        bits 59:56
                       wUPI_INIT_DONE,                                            //byte 6  bit 55
                       wCpu1BiosPostCmplt_n,                                      //        bit 54
                       wCpu0BiosPostCmplt_n,                                      //        bit 53
                       FM_PFR_POSTCODE_SEL_LVC25_N,                                     //        bit 52
                       wBMC_PWR_FAULT,                                            //        bit 51
                       wSCM_PWR_FAULT,                                            //        bit 50
                       wCPU_AUX_PWR_FLT,                                          //        bit 49
                       wSCM_BMC_AUX_PWR_FAULT,                                    //        bit 48
                       wLED_STATUS,                                               //byte 5
                       wSCMFPGATEST,                                              //byte 4
                       wSCMFPGAREV,                                               //byte 3
                       `MAIN_MINOR_VERSION,                                            //byte 2
                       `MAIN_MAJOR_VERSION,                                                  //byte 1
                       //1'b0,                                                    //byte 0  bit 7
                       wSCM_BMC_AUX_PWR_OK,
                       wFM_BMC_ONCTL_LVDS_N,                                      //        bit 6
                       PWRGD_CPU0_FPGA_LVC1 ? rRstPltRstPfrSyncSGPIO_n : 1'b0, //        bit 5
                       wInModular,                                                //        bit 4
                       rFmPartitionSel_SyncSGPIO,                                    //        bit 3
                       rFmDualParition_SyncSGPIO,                                 //        bit 2  
                       wPldHeartBeat,                                             //        bit 1
                       1'b0                                                       //        bit 0         //valid bit is now active low

                       }),
                     .oSData(SGPIO_MAIN_MOD_FPGA_DIN_R_LVC18),                    //Serial data output to SGPIO master
                     .oPData(wMain2ModPData)                                      //Parallel data to internal registers (slave)
					 );

   assign wMain2ModStartBit              = !wMain2ModPData[0];                                     //valid bit now is active low, so we invert here and use it inverted already
   assign wVAL_DBG_JUMPER_EN_N           = wMain2ModStartBit ? wMain2ModPData[1] : 1'b1 ;
   assign wS5With12V_n                   = wMain2ModStartBit ? wMain2ModPData[2] : 1'b1;

   assign wFM_PERST_TIMING_SEL           = wMain2ModStartBit ? wMain2ModPData[4] : 1'b0;
   assign wFmCpu0IntrpsrCablePrsnt       = wMain2ModStartBit ? wMain2ModPData[5] : 1'b0;

   assign wSMRJODone                     = wMain2ModStartBit ? wMain2ModPData[8] : 1'b0;
   assign wFM_BIOS_IMAGE_SWAP_N          = wMain2ModStartBit ? wMain2ModPData[9] : 1'b0;

   assign wFmCpu1IntrpsrCablePrsnt       = wMain2ModStartBit ? wMain2ModPData[15] : 1'b0;

   assign wModularPrsnt                  = wMain2ModStartBit ? wMain2ModPData[18] : 1'b0;
   assign wPfrGlobalAck                  = wMain2ModStartBit ? wMain2ModPData[19] : 1'b0;
   assign wLegacyNode                    = wMain2ModStartBit ? wMain2ModPData[20] : 1'b1;
   assign wHPfrEna                       = wMain2ModStartBit ? wMain2ModPData[21] : 1'b0;
   assign wFM_STANDALONE_MODE_N          = wMain2ModStartBit ? wMain2ModPData[22] : 1'b0;
   assign wFM_4S_8S_MODE_N               = wMain2ModStartBit ? wMain2ModPData[23] : 1'b0;

   assign wFM_NODE_ID0                   = wMain2ModStartBit ? wMain2ModPData[24] : 1'b0;
   assign wFM_NODE_ID1                   = wMain2ModStartBit ? wMain2ModPData[25] : 1'b0;
   assign wFM_BMC_ONCTL_ACK_N            = wMain2ModStartBit ? wMain2ModPData[26] : 1'b1;
   assign wMCpu0PartitionId0             = wMain2ModStartBit ? wMain2ModPData[28] : 1'b0;      
   assign wMCpu1PartitionId0             = wMain2ModStartBit ? wMain2ModPData[30] : 1'b0;       //when in RP, it should be estimated from DUAL_PARTITION_N
   assign wFmCpu1SktOccBypass            = wMain2ModStartBit ? wMain2ModPData[41] : 1'b0;
   assign wSMPldUpgradeAck               = wMain2ModStartBit ? wMain2ModPData[42] : 1'b0;       //Acknowledge from Secondary/Modular PLD to enable Remote Image Upgrade

   assign wFM_GLBRST_HALT_MODE_MOD       = wMain2ModStartBit ? wMain2ModPData[44] : 1'b0;   //	bit 44 From CCB95 Implementation for Global Reset Halt Mode

   assign wFM_RST_PERST_BIT3_LVC25        = wMain2ModStartBit ? wMain2ModPData[45] : 1'b1;       //	bit 43 
   assign FM_DUAL_PARTITION_HDR_LVC25_N  = wMain2ModStartBit ? wMain2ModPData[46] : 1'b1;       //	bit 43 

   assign wFM_HPM_STBY_RDY_ACK           = wMain2ModStartBit ? wMain2ModPData[48] : 1'b0;       // for Sync HPM_STBY_RDY in Modular Platform

   assign wFM_PCIE_FV_BIF_EN             = wMain2ModStartBit ? wMain2ModPData[49] : 1'b0;
   
   assign wMBVR_ready_ack                = wMain2ModStartBit ? wMain2ModPData[50] : 1'b0;     // MBVR flow for Modular

   assign RST_PLTRST_CPU0_PLD_LVC18_N = wInModular ? wRstCpu0PltrstSyncFpgaSync2M_n : rRstPltRstPfrSync2M_n;   //if In Modular, use the input pin coming from the Modular PLD, if in RP, we use what is received from LVDS
   assign wFM_BMC_ONCTL_N = wFM_BMC_ONCTL_ACK_N;

   assign wPfrLocalSync        = wInModular ? wFmHpfrOut_sync2M : 1'b0;
   assign wPfrGlobalAck_toLVDS = wInModular ? wPfrGlobalAck : 1'b0;

`else // !`ifdef SECONDARY_FPGA

   assign RST_PLTRST_CPU0_PLD_LVC18_N = rRstPltRstPfrSync2M_n;
   assign wFM_BMC_ONCTL_N = wFM_BMC_ONCTL_LVDS_N;

`endif

   // PLTRST synchronizer
   always @ (posedge wClk_2M or negedge wRst_n)
     begin
        if (~wRst_n)
          begin
             rIblRdyMeta_n <= 1'b1;
             rIblRdySync2M_n <= 1'b1;
             rRstPltRstPfrMeta_n <= 1'b0;
             rRstPltRstPfrSync2M_n <= 1'b0;
          end
        else if (wClk_2M)
          begin
             rIblRdyMeta_n <= wIBL_RDY_N; 
             rIblRdySync2M_n <= rIblRdyMeta_n;

             rRstPltRstPfrMeta_n <= wRST_PLTRST_CPU0_PLD_LVC18_N;
             rRstPltRstPfrSync2M_n <= rRstPltRstPfrMeta_n;
          end
     end // always @ (posedge wClk_2M or negedge wRst_n)



   // PLTRST synchronizer
   always @ (posedge SGPIO_MAIN_MOD_FPGA_CLK_LVC18 or negedge wRst_n)
     begin
        if (~wRst_n)
          begin
		     rMbvrReadySync_SyncSGPIO               <= 1'b0;
             rRstPltRstPfrMeta2_n                   <= 1'b0;
             rRstPltRstPfrSyncSGPIO_n               <= 1'b0;
			 rFmDualPartitionQs_n_SyncSGPIO         <= 1'b0;
			 rFmDualPartitionQs_n_r1SyncSGPIO       <= 1'b0;
											        
			 rFmHpmStbyRdy_SyncSGPIO                <= 1'b0;
			 rRstPltrstCpu1PldR_n_SyncSGPIO         <= 1'b0;
			 rFmAsdEnDet_SyncSGPIO                  <= 1'b0;
			 rPwrgdPvnnMainCpu1_SyncSGPIO           <= 1'b0;
			 rPwrgdPvnnMainCpu0_SyncSGPIO           <= 1'b0;
			 rPwrgdCpu1Fpga_SyncSGPIO               <= 1'b0;
			 rPwrgdCpu0S0PwrokR_SyncSGPIO           <= 1'b0;
			 rFmThermtripCpu1LedLatched_SyncSGPIO   <= 1'b0;
			 rFmThermtripCpu1LedLatched_SyncSGPIO   <= 1'b0;
			 rHCpu1CaterrR2_n_SyncSGPIO             <= 1'b1;
			 rHCpu0CaterrR2_n_SyncSGPIO             <= 1'b1;
			 rFmPartitionSel_SyncSGPIO              <= 1'b0;
			 rFmDualParition_SyncSGPIO              <= 1'b0;
			 rFmHpmStbyRdy_r1SyncSGPIO              <= 1'b0;
			 rRstPltrstCpu1PldR_n_r1SyncSGPIO       <= 1'b0;
			 rFmAsdEnDet_r1SyncSGPIO                <= 1'b0;
			 rPwrgdPvnnMainCpu1_r1SyncSGPIO         <= 1'b0;
			 rPwrgdPvnnMainCpu0_r1SyncSGPIO         <= 1'b0;
			 rPwrgdCpu1Fpga_r1SyncSGPIO             <= 1'b0;
			 rPwrgdCpu0S0PwrokR_r1SyncSGPIO         <= 1'b0;
			 rFmThermtripCpu1LedLatched_r1SyncSGPIO <= 1'b0;
			 rFmThermtripCpu1LedLatched_r1SyncSGPIO <= 1'b0;
			 rHCpu1CaterrR2_n_r1SyncSGPIO           <= 1'b1;
			 rHCpu0CaterrR2_n_r1SyncSGPIO           <= 1'b1;
			 rFmPartitionSel_r1SyncSGPIO            <= 1'b0;
			 rFmDualParition_r1SyncSGPIO            <= 1'b0;
			 rPwrgdCpu0PltAuxPwrgdFpga_r1SyncSGPIO  <= 1'b0;
			 rRstCpu0_n_r1SyncSGPIO                 <= 1'b0;

          end
        else if (SGPIO_MAIN_MOD_FPGA_CLK_LVC18)
          begin
		     rMbvrReadySync_r1SyncSGPIO             <= wMBVR_ready_sync;
             rRstPltRstPfrMeta2_n                   <= wRST_PLTRST_CPU0_PLD_LVC18_N;
             rRstPltRstPfrSyncSGPIO_n               <= rRstPltRstPfrMeta2_n;

			 rFmDualPartitionQs_n_r1SyncSGPIO       <= wFM_DUAL_PARTITION_QS_LVC3_N;
			 rFmDualPartitionQs_n_SyncSGPIO         <= rFmDualPartitionQs_n_r1SyncSGPIO;
			 rFmHpmStbyRdy_r1SyncSGPIO              <= wFM_HPM_STBY_RDY_LVC18;
             rRstPltrstCpu1PldR_n_r1SyncSGPIO       <= RST_PLTRST_CPU1_PLD_R_LVC1_N;
             rFmAsdEnDet_r1SyncSGPIO                <= wFM_ASD_EN_DET_LVC3;
             rPwrgdPvnnMainCpu1_r1SyncSGPIO         <= wPWRGD_PVNN_MAIN_CPU1_FF && FM_PVNN_AUX_CPU1_LVC3_R_EN;
             rPwrgdPvnnMainCpu0_r1SyncSGPIO         <= wPWRGD_PVNN_MAIN_CPU0_FF && FM_PVNN_AUX_CPU0_EN_R_LVC25;
             rPwrgdCpu1Fpga_r1SyncSGPIO             <= PWRGD_CPU1_FPGA_LVC1;
             rPwrgdCpu0S0PwrokR_r1SyncSGPIO         <= PWRGD_CPU0_S0_PWROK_LVC1_R;
			 rFmThermtripCpu1LedLatched_r1SyncSGPIO <= oFM_THERMTRIP_CPU1_LED_LATCHED; 
			 rFmThermtripCpu0LedLatched_r1SyncSGPIO <= oFM_THERMTRIP_CPU0_LED_LATCHED; 
             rHCpu1CaterrR2_n_r1SyncSGPIO           <= H_CPU1_CATERR_LVC1_R2_N || !wPWRGD_PVNN_MAIN_CPU1_FF;
             rHCpu0CaterrR2_n_r1SyncSGPIO           <= H_CPU0_CATERR_LVC1_R2_N || !wPWRGD_PVNN_MAIN_CPU0_FF;
             rFmPartitionSel_r1SyncSGPIO            <= wFM_PARTITION_SEL_LVC3;
             rFmDualParition_r1SyncSGPIO            <= wFM_DUAL_PARTITION_LVC3_N;
			 rPwrgdCpu0PltAuxPwrgdFpga_r1SyncSGPIO  <= PWRGD_CPU0_PLT_AUX_PWRGD_FPGA_LVC18_R;
			 rRstCpu0_n_r1SyncSGPIO                 <= RST_CPU0_LVC1_R_N;
												    
             rMbvrReadySync_SyncSGPIO               <= rMbvrReadySync_r1SyncSGPIO;
             rFmHpmStbyRdy_SyncSGPIO                <= rFmHpmStbyRdy_r1SyncSGPIO;
             rRstPltrstCpu1PldR_n_SyncSGPIO         <= rRstPltrstCpu1PldR_n_r1SyncSGPIO;
             rFmAsdEnDet_SyncSGPIO                  <= rFmAsdEnDet_r1SyncSGPIO;
             rPwrgdPvnnMainCpu1_SyncSGPIO           <= rPwrgdPvnnMainCpu1_r1SyncSGPIO;
             rPwrgdPvnnMainCpu0_SyncSGPIO           <= rPwrgdPvnnMainCpu0_r1SyncSGPIO;
             rPwrgdCpu1Fpga_SyncSGPIO               <= rPwrgdCpu1Fpga_r1SyncSGPIO;
             rPwrgdCpu0S0PwrokR_SyncSGPIO           <= rPwrgdCpu0S0PwrokR_r1SyncSGPIO;
             rFmThermtripCpu1LedLatched_SyncSGPIO   <= rFmThermtripCpu1LedLatched_r1SyncSGPIO;
             rFmThermtripCpu0LedLatched_SyncSGPIO   <= rFmThermtripCpu0LedLatched_r1SyncSGPIO;
             rHCpu1CaterrR2_n_SyncSGPIO             <= rHCpu1CaterrR2_n_r1SyncSGPIO;
             rHCpu0CaterrR2_n_SyncSGPIO             <= rHCpu0CaterrR2_n_r1SyncSGPIO;
             rFmPartitionSel_SyncSGPIO              <= rFmPartitionSel_r1SyncSGPIO;
             rFmDualParition_SyncSGPIO              <= rFmDualParition_r1SyncSGPIO;
			 rPwrgdCpu0PltAuxPwrgdFpga_SyncSGPIO    <= rPwrgdCpu0PltAuxPwrgdFpga_r1SyncSGPIO;
			 rRstCpu0_n_SyncSGPIO                   <= rRstCpu0_n_r1SyncSGPIO;

          end
     end


   assign wHpmStbyRst_n = FM_HPM_STBY_RST_LVC18_N;
   
   assign wI2CSecondaryDataIn = SMB_DEBUG_MPLD_LVC3_SDA;
   assign SMB_DEBUG_MPLD_LVC3_SDA  = wI2CSecondaryDataOe ? 1'b0 : 1'bZ;
   assign wI2CSecondaryClkIn  = SMB_DEBUG_MPLD_LVC3_SCL;
   assign SMB_DEBUG_MPLD_LVC3_SCL  = wI2CSecondaryClkOe ? 1'b0 : 1'bZ;

    //I2C Master Wrapper translates AVMM to I2C and bridge memory map access to Secondary CPLD.
    i2c_mst_wrapper   i2c_mst_wrapper_inst
      (
       .clk                       ( wTxCoreClk                     ),
       .reset                     ( ~wTxPllLock                    ),
       //avmm connected to MUX select
       .avmm_address              ( wSecondaryAddress              ),
       .avmm_write                ( wSecondaryWrite                ),
       .avmm_writedata            ( wSecondaryWriteData            ),
       .avmm_read                 ( wSecondaryRead                 ),
       .avmm_readdata             ( wSecondaryReadData             ),
       .avmm_readdatavalid        ( wSecondaryReadDataValid        ),
       .avmm_waitrequest          ( wSecondaryWaitReq              ),
       .avmm_byteenable           ( wSecondaryByteEna              ),
       //i2c interface to debug CPLD
       .i2c_debug_data_in         ( wI2CSecondaryDataIn            ),
       .i2c_debug_clk_in          ( wI2CSecondaryClkIn             ),
       .i2c_debug_data_oe         ( wI2CSecondaryDataOe            ),
       .i2c_debug_clk_oe          ( wI2CSecondaryClkOe             ),
       //IIC_MM access error report
       .invalid_access_dbg        ( invalid_access_dbg             )
       );

// signals to/from global_csr should be sync'd
wire [31:0] adr_cntr1;
wire [31:0] adr_cntr2;
wire [3:0]  pwr_err_source_sync;
wire [3:0]  post_code_sync;
wire        pwr_restart_clear_sync;
wire        force_err_clear_sync;
wire        pwr_restart_sync;
wire        glbrst_status;
wire        glbrst_status_n;
wire        glbrst_sync;
assign      wsel_mux_dbg = 32'd0;
wire [31:0] wstatus_pwr_seq_1_sync;
wire [31:0] wstatus_pwr_seq_2_sync;
wire [31:0] wstatus_pwr_seq_3_sync;
wire [31:0] wstatus_pwr_seq_4_sync;

// synchronize Global CSR inputs to wTxCoreClk
sync_level_bus #(.WIDTH(4)) sync_perr  (.clk (wTxCoreClk), .sync_in(pwr_err_source),           .sync_out(pwr_err_source_sync));
sync_level_bus #(.WIDTH(4)) sync_code  (.clk (wTxCoreClk), .sync_in(wMASTER_POST_CODE),        .sync_out(post_code_sync));
sync_level_bus #(.WIDTH(1)) sync_rclr  (.clk (wTxCoreClk), .sync_in(pwr_restart_clear),        .sync_out(pwr_restart_clear_sync));
sync_level_bus #(.WIDTH(1)) sync_fclr  (.clk (wTxCoreClk), .sync_in(force_to_enter_err_clear), .sync_out(force_err_clear_sync));
sync_level_bus #(.WIDTH(32)) sync_adr1 (.clk (wTxCoreClk), .sync_in(ADRcounter1),              .sync_out(adr_cntr1));
sync_level_bus #(.WIDTH(32)) sync_adr2 (.clk (wTxCoreClk), .sync_in(ADRcounter2),              .sync_out(adr_cntr2));
sync_level_bus #(.WIDTH(1)) sync_glbr  (.clk (wTxCoreClk), .sync_in(wGLBRST_STATUS),           .sync_out(glbrst_status));
sync_level_bus #(.WIDTH(1)) sync_glbn  (.clk (wTxCoreClk), .sync_in(!FM_CPU0_GLB_RST_WARN_PLD_N_FF), .sync_out(glbrst_status_n));
sync_level_bus #(.WIDTH(1)) sync_glb2  (.clk (wTxCoreClk), .sync_in(wGlobalResetSync2M),       .sync_out(glbrst_sync));
sync_level_bus #(.WIDTH(32)) sync_ws1  (.clk (wTxCoreClk), .sync_in(wstatus_pwr_seq_1),        .sync_out(wstatus_pwr_seq_1_sync));
sync_level_bus #(.WIDTH(32)) sync_ws2  (.clk (wTxCoreClk), .sync_in(wstatus_pwr_seq_2),        .sync_out(wstatus_pwr_seq_2_sync));
sync_level_bus #(.WIDTH(32)) sync_ws3  (.clk (wTxCoreClk), .sync_in(wstatus_pwr_seq_3),        .sync_out(wstatus_pwr_seq_3_sync));
sync_level_bus #(.WIDTH(32)) sync_ws4  (.clk (wTxCoreClk), .sync_in(wstatus_pwr_seq_4),        .sync_out(wstatus_pwr_seq_4_sync));


// synchronize Global CSR outputs to proper clock domain
sync_level_bus #(.WIDTH(1)) sync_prs  (.clk (wClk_2M), .sync_in(pwr_restart),  .sync_out(pwr_restart_sync));
//
    //main global csr
    cpu_global_csr  main_global_csr_inst
    (
        .clk                      ( wTxCoreClk                     ),
        .reset                    ( !wTxPllLock                    ),
        //avmm interface
        .avmm_address             ( main_csr_address               ),
        .avmm_write               ( main_csr_write                 ),
        .avmm_writedata           ( main_csr_writedata             ),
        .avmm_read                ( main_csr_read                  ),
        .avmm_readdata            ( main_csr_readdata              ),
        .avmm_readdatavalid       ( main_csr_readdatavalid         ),
        .avmm_waitrequest         ( main_csr_waitrequest           ),
        .avmm_byteenable          ( main_csr_byteenable            ),
        // inputs
        .mcsi_aligned             ( wMcsiAligned                   ), // signal already synchronous to MCSI clock
        .pwr_err_source           ( pwr_err_source_sync            ),
        .rstate                   ( post_code_sync                 ),
        .pwr_restart_clear        ( pwr_restart_clear_sync         ),
        .force_to_enter_err_clear ( force_err_clear_sync           ),
        .ADRcounter1              ( adr_cntr1                      ),
        .ADRcounter2              ( adr_cntr2                      ),
        // Hold off Global Reset
        .iGLBRST_STATUS           ( glbrst_status                  ),
        .iGLBRST_CPU              ( glbrst_status_n                ),
        .iGLBRST_BMC              ( glbrst_sync                    ),
        .iSEL_MUL_PWRSEQ_MEASURE  ( wsel_mux_dbg                   ),
        .status_pwr_seq_1         ( wstatus_pwr_seq_1_sync         ),
        .status_pwr_seq_2         ( wstatus_pwr_seq_2_sync         ),
        .status_pwr_seq_3         ( wstatus_pwr_seq_3_sync         ),
        .status_pwr_seq_4         ( wstatus_pwr_seq_4_sync         ),
        .pwr_restart              ( pwr_restart                    ),
        .invalid_access           ( invalid_access_cpu_glb         ),
        .force_to_enter_err       ( force_to_enter_err             ), 
        .oGLBRST_HOLD_OFF_EN      ( wGLBRST_HOLD_OFF_EN            ), 
        .oGLBRST_HOLD_OFF         ( wGLBRST_HOLD_OFF               ),
        .oNMI_SEL_CPU_eSPI        ( wNMI_SEL_CPU_eSPI              )
    );

    //ADC Wrapper
    adc_wrapper adc_wrapper_inst
    (
      .iClk                       ( wClk_25M_adc                   ),
      .iRst_n                     ( wAdcPllLocked                  ),

      .isys_clk                   ( wTxCoreClk                     ),
      .isys_rst_n                 ( wTxPllLock                     ),

      //ADC realted
      .iclk_2m_adc                ( wClk_2M_adc                    ),
      .iadc_pll_locked            ( wAdcPllLocked                  ),
      //AVMM interface
      .avmm_address               ( adc_csr_address                ),
      .avmm_write                 ( adc_csr_write                  ),
      .avmm_writedata             ( adc_csr_writedata              ),
      .avmm_read                  ( adc_csr_read                   ),
      .avmm_readdata              ( adc_csr_readdata               ),
      .avmm_readdatavalid         ( adc_csr_readdatavalid          ),
      .avmm_waitrequest           ( adc_csr_waitrequest            ),
      .avmm_byteenable            ( adc_csr_byteenable             ),
      //error report
      .invalid_access             ( invalid_access_adc             )
    );

   //--------------------------------------------------------------------------------------------------------------

 
assign FM_CPU0_PWRBTN_FPGA_R_LVC18_N  = wFM_CPU0_PWRBTN_FPGA_R_LVC18_N;
assign RST_CPU0_RSTBTN_FPGA_LVC18_R_N = wFmRstCpu0RstBtnFpgaSync2M_n;

   assign FM_DBG_MUX_TDO_CTRL = wCPU1_AUX_PWR_OK ? (wFmCpu1SktOccBypass ? 1'b1 : 1'b0 ) : 1'b1;
   
   
   assign FM_SYS_THROTTLE_R_LVC3_N = wFM_SYS_THROTTLE_R_N ?  1'bZ : 1'b0;
   assign RST_BMC_HSBP_MUX_LVC18_N = wRST_BMC_HSBP_MUX_N ?  1'bZ : 1'b0;
   assign RST_BMC_PCIE_MUX_R_LVC18_N = wRST_BMC_PCIE_MUX_R_N ?  1'bZ : 1'b0;



   assign wBoardId = {FM_BOARD_SKU_ID5, FM_BOARD_SKU_ID4, FM_BOARD_SKU_ID3, FM_BOARD_SKU_ID2, FM_BOARD_SKU_ID1, FM_BOARD_SKU_ID0};   

   assign wInModular = (wBoardId == 6'h25 || wBoardId == 6'h3B) ? 1'b1 : 1'b0;
   assign wInRP      = (wBoardId == 6'h20 || wBoardId == 6'h3A) ? 1'b1 : 1'b0;

   assign wFM_BOARD_REV_ID = {FM_BOARD_REV_ID2, FM_BOARD_REV_ID1, FM_BOARD_REV_ID0};


   //other assignments for initial board stages

   assign wIBL_RDY_N = (wInModular && !wLegacyNode && !wCpu0IntrPrsnt_n ? 1'b0 :  FM_CPU0_REFCLK_RDY_R_FPGA_LVC18_OD);

    assign wFM_DUAL_PARTITION_LVC3_N = 1'b1;

   wire RstPldPcieCpu0DcscmPerst_n_sync2M;
   level_sync dcscmPerst2M (.clk(wClk_2M), .signal_in(RST_PLD_PCIE_CPU0_DCSCM_PERST_LVC3_R_N ), .signal_sync(RstPldPcieCpu0DcscmPerst_n_sync2M));
   
   assign FM_DUAL_PARTITION_LVC3_N = ((wInRP && wFM_BOARD_REV_ID == 3'h0) || (wInModular && wFM_BOARD_REV_ID == 3'h0 || wInModular && wFM_BOARD_REV_ID == 3'h1)) ? 1'b1 : RstPldPcieCpu0DcscmPerst_n_sync2M;

   //Partition Sel output is always HIGHZ if in Modular, but internal logic should point to partition 0 -> else, we assume RP and if not in partition, it must be always LOW, if we are, we take it from jumper

   wire RstPldPcieCpu0X16Perst_n_sync2M;
   level_sync x16Perst2M (.clk(wClk_2M), .signal_in(RST_PLD_PCIE_CPU0_x16_PERST_LVC3_R_N ), .signal_sync(RstPldPcieCpu0X16Perst_n_sync2M));

   assign wFM_PARTITION_SEL_LVC3   = wInModular ? 1'b0 : !wFM_DUAL_PARTITION_LVC3_N && FM_PARTITION_SEL_HDR_LVC25;
   assign FM_PARTITION_SEL_LVC3    = wInModular ? 1'bZ : wFM_BOARD_REV_ID == 3'h0 ? wFM_PARTITION_SEL_LVC3 : RstPldPcieCpu0X16Perst_n_sync2M;

   assign wFM_DUAL_PARTITION_QS_LVC3_N = ({wFM_CPU1_SKTOCC_LVT3_PLD_N,wFM_CPU0_SKTOCC_LVT3_PLD_N} == 2'b00 ? wPWRGD_PVNN_MAIN_CPU0_FF && wPWRGD_PVNN_MAIN_CPU1_FF : 1'b0);

// synchronize for output timing analysis
wire dual_part_in;
wire dual_partition_sync; 
assign dual_part_in = wInModular ? 1'bZ : wInRP && wFM_BOARD_REV_ID == 3'h0 ? wFM_DUAL_PARTITION_QS_LVC3_N : 1'bZ;
level_sync sync_part (.clk(wClk_2M), .signal_in(dual_part_in ), .signal_sync(dual_partition_sync ));   

    assign FM_DUAL_PARTITION_QS_LVC3_N = dual_partition_sync;

   assign FM_PECI_SEL_0_LVC3_N = wFM_DUAL_PARTITION_LVC3_N ? (wFM_CPU0_SKTOCC_LVT3_PLD_N ? 1'b1 : !wPWRGD_PVNN_MAIN_CPU0_FF) : wFM_PARTITION_SEL_LVC3;
   assign FM_PECI_SEL_1_LVC3_N = wFM_DUAL_PARTITION_LVC3_N ? (wFM_CPU1_SKTOCC_LVT3_PLD_N ? 1'b1 : !wPWRGD_PVNN_MAIN_CPU1_FF) : !wFM_PARTITION_SEL_LVC3;
                                 

   //Used selector is already qualified by if Modular, and if in partition or not, so we can simplify the equation


   assign FM_CPU0_GPIO0_RSVD_LVC1          = wPWRGD_PVNN_MAIN_CPU0_FF ? (RST_PLTRST_CPU0_PLD_LVC18_N ? 1'bZ : (wInModular ? wMCpu0PartitionId0 : 1'b0)) : 1'bZ;        //in Modular, follows what comes from Misc IO thru Modular PLD, in RP, it should be always LOW

   assign FM_CPU1_GPIO0_PARTITION_ID0_LVC1 = wPWRGD_PVNN_MAIN_CPU1_FF ? (RST_PLTRST_CPU0_PLD_LVC18_N ? 1'bZ : (wInModular ? wMCpu1PartitionId0 : !wFM_DUAL_PARTITION_LVC3_N)) : 1'bZ;        //in Modular, follows what comes from Misc IO thru Modular PLD, in RP, depends on Dual Partition Config (if Partion, HIGH, else LOW)


   //For BMCINIT, only checking for INIT_DISABLE jumper, if not disabled, send whatever comes from LVDS, otherwise HIGHZ signals to take value from Board


   assign H_CPU0_BMCINIT_LVC1_R = wPWRGD_PVNN_MAIN_CPU0_FF ? (wFM_BMCINIT_DISABLE_LVC25_N ? wFM_BMC_BMCINIT : 1'bZ) : 1'bZ;
   assign H_CPU1_BMCINIT_LVC1_R = wPWRGD_PVNN_MAIN_CPU1_FF ? (wFM_BMCINIT_DISABLE_LVC25_N ? wFM_BMC_BMCINIT : 1'bZ) : 1'bZ;

   
   
   assign FM_CPU1_TIMED_GPIO0_LVC1 = 1'bZ ;
   assign FM_CPU1_FRMAGENT_LVC1 = wPWRGD_PVNN_MAIN_CPU0_FF ? (wInModular ? 1'b0 : !wFM_DUAL_PARTITION_LVC3_N) : 1'b0;

   //Used selector is already qualified by if Modular, and if in partition or not, so we can simplify the equation


   assign FM_CPU1_TIMED_GPIO1_LVC1 = 1'bZ ;
   assign FM_CPU0_TIMED_GPIO1_LVC1 = 1'bZ ;
   assign FM_CPU0_TIMED_GPIO0_LVC1 = 1'bZ ;

   assign FM_TS3DS10224_ENA_LVC25_OD = 1'b1;
wire cpu1_s0_pwrok; 
level_sync sync_s0 (.clk(wClk_20M), .signal_in(PWRGD_CPU1_S0_PWROK_LVC1_R ), .signal_sync(cpu1_s0_pwrok));   
   assign FM_TS3DS10224_ENB_LVC25_OD = !wFM_CPU0_SKTOCC_LVT3_PLD_N && !wFM_CPU1_SKTOCC_LVT3_PLD_N && cpu1_s0_pwrok ? 1'b1 : 1'b0;    //adding CPU1 S0 PWROK signal to make sure the clock input to non-legacy CPU is not clocking before the SOC is ON

   assign FM_S3M_CPU0_CPLD_CONFIG_LVC3_N = 1'bZ;                                
   assign FM_GPIO_XDP_SKT_SEL_LVC3 = 1'b0;                                      
   assign SGPIO_IDV_DIN_R_LVC3 = 1'b0;
   assign FM_S3M_CPU1_CPLD_CONFIG_LVC3_N = 1'bZ;

   assign FM_PWR_LED_R_N = !wFM_SLPS4_CPU0_CPU_PLD_N;

   

    assign wCPU_AUX_PWRGD_Partition_Sel = FM_GPIO_XDP_SKT_SEL_LVC3 ?  PWRGD_CPU1_PLT_AUX_PWRGD_FPGA_LVC18: PWRGD_CPU0_PLT_AUX_PWRGD_FPGA_LVC18_R;

    assign FM_DBP_JTAG_MUX_CPU0_LVC3_R_EN = wInModular ? 1'bZ : wCPU0_AUX_PWR_OK && (!FM_GPIO_XDP_SKT_SEL_LVC3 || wFM_DUAL_PARTITION_LVC3_N);
    assign FM_DBP_JTAG_MUX_CPU1_LVC3_R_EN = wInModular ? 1'bZ : wCPU1_AUX_PWR_OK && ( FM_GPIO_XDP_SKT_SEL_LVC3 || wFM_DUAL_PARTITION_LVC3_N);
    
    
    
   
    always @(posedge wClk_2M or negedge wRst_n)
    begin
        if (!wRst_n)
        begin
            FM_DBG_AUX_LVC3_PWRGD <= 1'b0;
        end
        else
        begin
            if (wFM_DUAL_PARTITION_LVC3_N)//1 socket and 2 sockets present
            begin
               FM_DBG_AUX_LVC3_PWRGD <= PWRGD_CPU0_PLT_AUX_PWRGD_FPGA_LVC18_R;
            end
            else if (!wFM_DUAL_PARTITION_LVC3_N)
            begin
                FM_DBG_AUX_LVC3_PWRGD <= wCPU_AUX_PWRGD_Partition_Sel;
            end
        end
    end

   assign FM_CPU0_EDSFFX4_LED_LVC3_EN = 1'b1;
   assign FM_CPU1_ADR_TRIGGER_LVC18_N = PWRGD_CPU1_PLT_AUX_PWRGD_FPGA_LVC18 ? 1'b1 : 1'bZ;
   assign FM_CPU1_S5_PWR_RETAINED_R = 1'b0;
   assign FM_CPU1_PWRBTN_LVC18_R_N = PWRGD_CPU1_PLT_AUX_PWRGD_FPGA_LVC18 ? FM_PWR_BTN_CPU1_LVC25_N : 1'bZ;                //temporal assignment and may require glitch filtering
   assign RST_CPU1_RSTBTN_LVC18_R_N = PWRGD_CPU1_PLT_AUX_PWRGD_FPGA_LVC18 ? FM_RST_BTN_CPU1_LVC25_N : 1'bZ;               //temporal assignment and may require glitch filtering
   assign IRQ_ESPI_CPU1_ALERT1_FPGA_R_LVC18_N = 1'bZ;


 
// synchronize for output timing analysis
wire irq_cpu0_wake_in;
wire irq_cpu0_wake_sync; 
wire irq_cpu1_wake_in;
wire irq_cpu1_wake_sync; 
    
assign irq_cpu0_wake_in = PWRGD_CPU0_PLT_AUX_PWRGD_FPGA_LVC18_R ? (wFM_DUAL_PARTITION_LVC3_N ? (IRQ_CPU0_WAKE_LVC3_R_N && IRQ_CPU1_WAKE_LVC3_R_N) : IRQ_CPU0_WAKE_LVC3_R_N) : 1'bZ;
assign irq_cpu1_wake_in = PWRGD_CPU1_PLT_AUX_PWRGD_FPGA_LVC18   ? (wFM_DUAL_PARTITION_LVC3_N ? 1'b1 : IRQ_CPU1_WAKE_LVC3_R_N) : 1'bZ;

level_sync sync_wake0 (.clk(wClk_2M), .signal_in(irq_cpu0_wake_in ), .signal_sync(irq_cpu0_wake_sync ));   
level_sync sync_wake1 (.clk(wClk_2M), .signal_in(irq_cpu1_wake_in ), .signal_sync(irq_cpu1_wake_sync ));   

assign IRQ_CPU0_WAKE_LVC18_R_N = irq_cpu0_wake_sync;
assign IRQ_CPU1_WAKE_LVC18_R_N = irq_cpu1_wake_sync;

   assign IRQ_ESPI_CPU0_ALERT1_FPGA_LVC18_N = wPwrgdCpu0PltAuxPwrgdFpga_SyncESPI ? wIRQ_ESPI_CPU0_ALERT1_FPGA_LVC18_N : 1'bZ;
   assign IRQ_ESPI_CPU0_ALERT0_FPGA_LVC18_N = 1'bZ;

   assign ESPI_CPU1_IO0_FPGA_R_LVC18 = 1'bZ;
   assign ESPI_CPU1_IO1_FPGA_R_LVC18 = 1'bZ;
   assign ESPI_CPU1_IO3_FPGA_R_LVC18 = 1'bZ;
   assign ESPI_CPU1_IO2_FPGA_R_LVC18 = 1'bZ;

   assign wRST_PLTRST_CPU0_TPM_PLD_LVC18_N = FM_CPU0_TPM_CONN_PRSNT_COD18_N ? RST_PLTRST_CPU0_PLD_LVC18_N : 1'b0;
   assign RST_PLTRST_CPU1_TPM_PLD_LVC18_N = wInModular ? 1'bZ : !wFM_DUAL_PARTITION_LVC3_N && RST_PLTRST_CPU1_PLD_R_LVC1_N;
   assign FM_HPM_STBY_RDY_LVC18 = wInModular ? wFM_HPM_STBY_RDY_ACK  : wFM_HPM_STBY_RDY_LVC18 ;  // for Sync HPM_STBY_RDY in Modular Platform 

   assign FM_CPU1_SOCKET_ID0_LVC1 = wPWRGD_PVNN_MAIN_CPU1_FF ? (wInModular ? 1'b1 : (wFM_DUAL_PARTITION_LVC3_N ? 1'b1 : 1'b0)) : 1'bZ;

   

   

   



   assign RST_CPU1_RTCRST_PLD_R_N = wFM_PARTITION_SEL_LVC3 ? (!wRST_CPU1_RTCRST_N ? 1'bZ : 1'b0) : 1'bZ;


wire FmCpu0Edsffx4Prsnt0_n_sync100M;
level_sync sync_cpu0_edsff_prsnt (.clk(wClk_100M), .signal_in(FM_CPU0_EDSFFX4_PRSNT0_LVC3_N ), .signal_sync(FmCpu0Edsffx4Prsnt0_n_sync100M )); 

   assign RST_CPU0_PE1_EDSFFX4_PERST0_PLD_R_N = FmCpu0Edsffx4Prsnt0_n_sync100M ? 1'b0 : RST_PLD_PCIE_CPU0_DEV_PERST_LVC3_R_N;


    assign wGLBRST_STATUS                   = !FM_CPU0_GLB_RST_WARN_PLD_N_FF;
    assign wFM_GLBRST_HALT_MODE = wInModular ? wFM_GLBRST_HALT_MODE_MOD : FM_GLBRST_HALT_MODE_RP;

    assign wFM_SKT0_FAULT_LED_SECFPGA = ((wGLBRST_HOLD_OFF_EN && wGLBRST_HOLD_OFF || wFM_GLBRST_HALT_MODE) && wGLBRST_STATUS) ? wPldHeartBeat : wFM_SKT0_FAULT_LED;


wire i2c_main_data_in, i2c_main_data_oe, i2c_main_clk_in, i2c_main_clk_oe;

	  //This i2c_slave is connected to main debug
assign i2c_main_data_in = SMB_HOST_MAINFPGA_LVC3_SDA;
assign SMB_HOST_MAINFPGA_LVC3_SDA = i2c_main_data_oe ? 1'b0 : 1'bz;
assign i2c_main_clk_in  = SMB_HOST_MAINFPGA_LVC3_SCL;
assign SMB_HOST_MAINFPGA_LVC3_SCL = i2c_main_clk_oe ? 1'b0 : 1'bz;


	// This module recive of I2c and convert to avmm for debug
	i2c_slave_main_wrapper i2c_slave_main_wrapper_inst
(
   .clk                 ( wTxCoreClk              ), 	//should use clock from LVDS_TX internal PLL
   .rst_n               ( !wTxPllLock             ),

   //IIC interface
   .i2c_data_in         ( i2c_main_data_in        ),
   .i2c_clk_in          ( i2c_main_clk_in         ),
   .i2c_data_oe         ( i2c_main_data_oe        ),
   .i2c_clk_oe          ( i2c_main_clk_oe         ),

   //AVMM interface
	.waitrequest        ( avmm_host_mst_waitrq    ),
	.readdatavalid      ( avmm_host_mst_rdvalid   ),
	.readdata           ( avmm_host_mst_rdata     ),
	.address            ( avmm_host_mst_addr      ),
	.write              ( avmm_host_mst_write     ),
	.writedata          ( avmm_host_mst_wdata     ),
	.read               ( avmm_host_mst_read      ),
	.byteenable         ( avmm_host_mst_byteen    )
);

// This module connect to 2 master to 5 slaves avmmm
avmm_mux_2Masters_To_5Slaves
#(    // adress low and high of each slave.
     .SLV1_ADDR_LOW     ( 32'h0000                ),
     .SLV1_ADDR_High    ( 32'h00FF                ),
     .SLV2_ADDR_LOW     ( 32'h0100                ),
     .SLV2_ADDR_High    ( 32'h01FF                ),
     .SLV3_ADDR_LOW     ( 32'h0200                ),
     .SLV3_ADDR_High    ( 32'h02FF                ),
     .SLV4_ADDR_LOW     ( 32'h8000                ),
     .SLV4_ADDR_High    ( 32'h9FFF                ),
     .SLV5_ADDR_LOW     ( 32'hA000                ),
     .SLV5_ADDR_High    ( 32'hFFFF                )
  )
avmm_mux_2Masters_To_5Slaves_inst
	(
	//Clock and Reset
    .clk                ( wTxCoreClk              ),
    .rst_n              ( wTxPllLock              ),

    //AVMM_Master1, connected to I2C slave BMC AVMM
    .mst1_address       ( avmm_mst_addr           ),
    .mst1_write         ( avmm_mst_write          ),
    .mst1_writedata     ( avmm_mst_wdata          ),
    .mst1_read          ( avmm_mst_read           ),
    .mst1_readdata      ( avmm_mst_rdata          ),
    .mst1_readdatavalid ( avmm_mst_rdvalid        ),
    .mst1_waitrequest   ( avmm_mst_waitrq         ),
    .mst1_byteenable    ( avmm_mst_byteen         ),

	 //AVMM_Master2, connected to I2C slave main HOST
    .mst2_address       ( avmm_host_mst_addr      ),
    .mst2_write         ( avmm_host_mst_write     ),
    .mst2_writedata     ( avmm_host_mst_wdata     ),
    .mst2_read          ( avmm_host_mst_read      ),
    .mst2_readdata      ( avmm_host_mst_rdata     ),
    .mst2_readdatavalid ( avmm_host_mst_rdvalid   ),
    .mst2_waitrequest   ( avmm_host_mst_waitrq    ),
    .mst2_byteenable    ( avmm_host_mst_byteen    ),

   //AVMM_Slave_1, connect to cpu global csr
   .slv1_address        ( main_csr_address        ),
   .slv1_write          ( main_csr_write          ),
   .slv1_writedata      ( main_csr_writedata      ),
   .slv1_read           ( main_csr_read           ),
   .slv1_readdata       ( main_csr_readdata       ),
   .slv1_readdatavalid  ( main_csr_readdatavalid  ),
   .slv1_waitrequest    ( main_csr_waitrequest    ),
   .slv1_byteenable     ( main_csr_byteenable     ),
   .invalid_access_slv1 ( invalid_access_cpu_glb  ),

   //AVMM_Slave_2, connect to cpu mcsi internal CSR
   .slv2_address        ( mcsi_csr_address       ),
   .slv2_write          ( mcsi_csr_write         ),
   .slv2_writedata      ( mcsi_csr_writedata     ),
   .slv2_read           ( mcsi_csr_read          ),
   .slv2_readdata       ( mcsi_csr_readdata      ),
   .slv2_readdatavalid  ( mcsi_csr_readdatavalid ),
   .slv2_waitrequest    ( mcsi_csr_waitrequest   ),
   .slv2_byteenable     ( mcsi_csr_byteenable    ),
   .invalid_access_slv2 ( invalid_access_cpu_mcsi),

   //AVMM_Slave_3, connect to ADC CSR
   .slv3_address        ( adc_csr_address        ),
   .slv3_write          ( adc_csr_write          ),
   .slv3_writedata      ( adc_csr_writedata      ),
   .slv3_read           ( adc_csr_read           ),
   .slv3_readdata       ( adc_csr_readdata       ),
   .slv3_readdatavalid  ( adc_csr_readdatavalid  ),
   .slv3_waitrequest    ( adc_csr_waitrequest    ),
   .slv3_byteenable     ( adc_csr_byteenable     ),
   .invalid_access_slv3 ( invalid_access_adc     ),

   //AVMM_Slave_4, connect to secondary FPGA
   .slv4_address        ( wSecondaryAddress      ),
   .slv4_write          ( wSecondaryWrite        ),
   .slv4_writedata      ( wSecondaryWriteData    ),
   .slv4_read           ( wSecondaryRead         ),
   .slv4_readdata       ( wSecondaryReadData     ),
   .slv4_readdatavalid  ( wSecondaryReadDataValid),
   .slv4_waitrequest    ( wSecondaryWaitReq      ),
   .slv4_byteenable     ( wSecondaryByteEna      ),

   ////AVMM_Slave_5, connect to RJO
   .slv5_address        ( rjo_address            ),
   .slv5_write          ( rjo_write              ),
   .slv5_writedata      ( rjo_writedata          ),
   .slv5_read           ( rjo_read               ),
   .slv5_readdata       ( rjo_readdata           ),
   .slv5_readdatavalid  ( rjo_readdatavalid      ),
   .slv5_waitrequest    ( rjo_waitrequest        ),
   .slv5_byteenable     ( rjo_byteenable         ),

   .status_reg          (                         ),
   .status_reg_mm       ( 4'h0                    )
	);

// wires
wire wPLTRST_N, wSlpS3, wAUX_PWRGD_CPU, iCPU0_MEM_Done, iCPU1_MEM_Done, invalid_access_rjc;
wire PFR_FORCE_RECOVERY_RJC_N_Value, PFR_DEBUG_JUMPER_RJC_N_Value, FM_TTK_SPI_EN_RJC_N_Value, PFR_FORCE_RECOVERY_RJC_N_Override, PFR_DEBUG_JUMPER_RJC_N_Override, FM_TTK_SPI_EN_RJC_N_Override;

wire RSU_FlashBusy;

// Timing cleanup
// Synchronize all inputs to the RJO module
wire val_dbg_jumper_en;
wire rsu_flash_bsy;
wire rst20_n;
//
level_sync sync_dbgj  (.clk(wClk_20M), .signal_in(wVAL_DBG_JUMPER_EN_N ), .signal_sync(val_dbg_jumper_en));   
level_sync sync_rst20 (.clk(wClk_20M), .signal_in(wRst_n ),               .signal_sync(rst20_n));   

// This module drive to jumper override
  RJO_TOP

  #(
        .JUMPER_COUNT  (JUMPER_COUNT)

    )RJO_TOP_inst
(
 .Clock                             ( wClk_20M                           ),
 .Reset                             ( !rst20_n                           ),
 .FM_VAL_DBG_JUMPER_EN              ( val_dbg_jumper_en                  ),
 .T_Reset                           ( T_Reset                            ),
 .iPLTRST_N                         ( 1'b1                  ),
 .iSlpS3                            ( 1'b1                     ),
 .iAUX_PWRGD_CPU                    ( 1'b1             ),
 .JumperIn                          ( rCurrentValue                      ),
 .iCPU0_MEM_Done                    ( 1'b1             ),
 .iCPU1_MEM_Done                    ( 1'b1            ),
 .RSU_FlashBusy                     ( RSU_FlashBusy                      ),
 .JumperOut                         ( wOverrideValue                     ),
 .invalid_access                    ( invalid_access_rjc                 ),
 .FM_TTK_SPI_EN_RJC_N_Override      ( FM_TTK_SPI_EN_RJC_N_Override       ),
 .PFR_DEBUG_JUMPER_RJC_N_Override   ( PFR_DEBUG_JUMPER_RJC_N_Override    ),
 .PFR_FORCE_RECOVERY_RJC_N_Override ( PFR_FORCE_RECOVERY_RJC_N_Override  ),
 .FM_TTK_SPI_EN_RJC_N_Value         ( FM_TTK_SPI_EN_RJC_N_Value          ),
 .PFR_DEBUG_JUMPER_RJC_N_Value      ( PFR_DEBUG_JUMPER_RJC_N_Value       ),
 .PFR_FORCE_RECOVERY_RJC_N_Value    ( PFR_FORCE_RECOVERY_RJC_N_Value     ),
 // Interface conected to mux avmm_mux_2Masters_To_5Slaves_inst: sync to wTxCoreClk
 .avmm_write                        ( clk20_rjo_write                    ),
 .avmm_read                         ( clk20_rjo_read                     ),
 .avmm_address                      ( clk20_rjo_address                  ),
 .avmm_writedata                    ( clk20_rjo_writedata                ),
 .avmm_byteenable                   ( clk20_rjo_byteenable               ),
 .avmm_readvalid                    ( clk20_rjo_readdatavalid            ),
 .avmm_readdata                     ( clk20_rjo_readdata                 ),
 .avmm_waitrequest                  ( clk20_rjo_waitrequest              ),
 // RJO Flash 2:1 mux: sync to wClk_20M
 .avmm_csr_addr                     ( RJO_flash_csr_addr                 ),
 .avmm_csr_read                     ( RJO_flash_csr_read                 ),
 .avmm_csr_writedata                ( RJO_flash_csr_writedata            ),
 .avmm_csr_write                    ( RJO_flash_csr_write                ),
 .avmm_csr_readdata                 ( RJO_flash_csr_readdata             ),
 .avmm_data_addr                    ( RJO_flash_data_addr                ),
 .avmm_data_read                    ( RJO_flash_data_read                ),
 .avmm_data_writedata               ( RJO_flash_data_writedata           ),
 .avmm_data_write                   ( RJO_flash_data_write               ),
 .avmm_data_readdata                ( RJO_flash_data_readdata            ),
 .avmm_data_waitrequest             ( RJO_flash_data_waitrequest         ),
 .avmm_data_readdatavalid           ( RJO_flash_data_readdatavalid       ),
 .avmm_data_burstcount              ( RJO_flash_data_burstcount          ),
 .oOvDisable                        ( wOvEnable_n                        ),
 .rjo_ready                         (  rjo_ready                         )

 );

// from master to slave
level_sync sync_wr  (.clk(wClk_20M), .signal_in(rjo_write ), .signal_sync(clk20_rjo_write ));   
level_sync sync_rd  (.clk(wClk_20M), .signal_in(rjo_read ),  .signal_sync(clk20_rjo_read ));  

sync_level_bus #(.WIDTH(32)) sync_addr (.clk (wClk_20M), .sync_in(rjo_address),    .sync_out(clk20_rjo_address));
sync_level_bus #(.WIDTH(32)) sync_wd   (.clk (wClk_20M), .sync_in(rjo_writedata),  .sync_out(clk20_rjo_writedata));
sync_level_bus #(.WIDTH(4))  sync_be   (.clk (wClk_20M), .sync_in(rjo_byteenable), .sync_out(clk20_rjo_byteenable));

// from slave to master
level_sync sync_rdv                      (.clk(wTxCoreClk), .signal_in(clk20_rjo_readdatavalid ), .signal_sync(rjo_readdatavalid ));   
level_sync sync_wtr                      (.clk(wTxCoreClk), .signal_in(clk20_rjo_waitrequest ),   .signal_sync(rjo_waitrequest ));   
sync_level_bus #(.WIDTH(32))  sync_rdata (.clk(wTxCoreClk), .sync_in(clk20_rjo_readdata),         .sync_out(rjo_readdata));


   RJO_MAIN ProbeAndSource (
                            .source (flag_source)
                          
                            );
 
assign wRST_CPU0_RTCRST_PLD_R_N = 1'b1;
wire [2:0] cpu0_pkgid;
wire [2:0] cpu1_pkgid;
wire [1:0] perst;
wire bmcinit_dis;
wire rjc_jumper;
wire force_rec;
wire ttk_spi_en;
wire cpu0_auxpg;
wire pass_clr;
wire asd_en;
wire cpu0_sktocc;
wire cpu1_sktocc;
wire ps_en;
wire serial_boot;
wire adr_ext0;
wire adr_ext1;
wire cpu0_therm;
wire cpu1_therm;
wire cpu0_pltrst_tpm;
wire bmc_safs_20;

level_sync sync_rtc   (.clk(wClk_20M), .signal_in(wRST_CPU0_RTCRST_N ),                     .signal_sync(cpu0_rtcrst));   
level_sync sync_bmc   (.clk(wClk_20M), .signal_in(FM_BMCINIT_DISABLE_LVC25_N ),             .signal_sync(bmcinit_dis));   
level_sync sync_pid00 (.clk(wClk_20M), .signal_in(FM_CPU0_PKGID0 ),                         .signal_sync(cpu0_pkgid[0]));   
level_sync sync_pid01 (.clk(wClk_20M), .signal_in(FM_CPU0_PKGID1 ),                         .signal_sync(cpu0_pkgid[1]));   
level_sync sync_pid02 (.clk(wClk_20M), .signal_in(FM_CPU0_PKGID2 ),                         .signal_sync(cpu0_pkgid[2]));   
level_sync sync_pid10 (.clk(wClk_20M), .signal_in(FM_CPU1_PKGID0 ),                         .signal_sync(cpu1_pkgid[0]));   
level_sync sync_pid11 (.clk(wClk_20M), .signal_in(FM_CPU1_PKGID1 ),                         .signal_sync(cpu1_pkgid[1]));   
level_sync sync_pid12 (.clk(wClk_20M), .signal_in(FM_CPU1_PKGID2 ),                         .signal_sync(cpu1_pkgid[2]));   
level_sync sync_rjc   (.clk(wClk_20M), .signal_in(PFR_DEBUG_JUMPER_RJC_N_IN ),              .signal_sync(rjc_jumper));   
level_sync sync_rec   (.clk(wClk_20M), .signal_in(PFR_FORCE_RECOVERY_RJC_N_IN ),            .signal_sync(force_rec));   
level_sync sync_ttk   (.clk(wClk_20M), .signal_in(FM_TTK_SPI_EN_RJC_N_IN ),                 .signal_sync(ttk_spi_en));   
level_sync sync_per0  (.clk(wClk_20M), .signal_in(FM_RST_PERST_BIT0_LVC25 ),                .signal_sync(perst[0]));   
level_sync sync_per1  (.clk(wClk_20M), .signal_in(FM_RST_PERST_BIT1_LVC25 ),                .signal_sync(perst[1]));   
level_sync sync_aux0  (.clk(wClk_20M), .signal_in(wPWRGD_CPU0_PLT_AUX_PWRGD_FPGA_LVC18_R ), .signal_sync(cpu0_auxpg));   
level_sync sync_pwd   (.clk(wClk_20M), .signal_in(FM_PASSWORD_CLEAR_LVC25_N ),              .signal_sync(pass_clr));   
level_sync sync_asd   (.clk(wClk_20M), .signal_in(FM_ASD_EN_DET_LVC3 ),                     .signal_sync(asd_en));   
level_sync sync_skt0  (.clk(wClk_20M), .signal_in(FM_CPU0_SKTOCC_LVT3_PLD_N ),              .signal_sync(cpu0_sktocc));   
level_sync sync_skt1  (.clk(wClk_20M), .signal_in(FM_CPU1_SKTOCC_LVT3_PLD_N ),              .signal_sync(cpu1_sktocc));   
level_sync sync_psen  (.clk(wClk_20M), .signal_in(wFM_PS_EN_PLD_R_LVC3 ),                   .signal_sync(ps_en));   
level_sync sync_ser   (.clk(wClk_20M), .signal_in(FM_SERIAL_BOOT ),                         .signal_sync(serial_boot));   
level_sync sync_adrt0 (.clk(wClk_20M), .signal_in(FM_CPU0_ADR_EXT_TRIGGER_LVC25_N ),        .signal_sync(adr_ext0));   
level_sync sync_adrt1 (.clk(wClk_20M), .signal_in(FM_CPU1_ADR_EXT_TRIGGER_LVC25_N ),        .signal_sync(adr_ext1));   
level_sync sync_trip0 (.clk(wClk_20M), .signal_in(H_CPU0_THERMTRIP_FPGA_LVC1_R_N ),         .signal_sync(cpu0_therm));   
level_sync sync_trip1 (.clk(wClk_20M), .signal_in(H_CPU1_THERMTRIP_LVC1_R2_N ),             .signal_sync(cpu1_therm));   
level_sync sync_plt0  (.clk(wClk_20M), .signal_in(wRST_PLTRST_CPU0_TPM_PLD_LVC18_N ),       .signal_sync(cpu0_pltrst_tpm));   
level_sync sync_safs2 (.clk(wClk_20M), .signal_in(FM_CPU0_GPIO4_EAF_BMC_SAFS_SEL_LVC1 ),    .signal_sync(bmc_safs_20));   
  
   always@(*) begin
      rCurrentValue[0 ] =  wOvEnable_n  [0 ] ? cpu0_rtcrst              :  wOverrideValue[0 ];// pin rjo #1  address = 0x0C
      rCurrentValue[1 ] =  wOvEnable_n  [1 ] ? bmcinit_dis              :  wOverrideValue[1 ];// pin rjo #2  address = 0x10
      rCurrentValue[2 ] =  wOvEnable_n  [2 ] ? cpu0_pkgid[0]            :  wOverrideValue[2 ];// pin rjo #3  address = 0x14
      rCurrentValue[3 ] =  wOvEnable_n  [3 ] ? cpu0_pkgid[1]            :  wOverrideValue[3 ];// pin rjo #4  address = 0x18
      rCurrentValue[4 ] =  wOvEnable_n  [4 ] ? cpu0_pkgid[2]            :  wOverrideValue[4 ];// pin rjo #5  address = 0x1C
      rCurrentValue[5 ] =  wOvEnable_n  [5 ] ? cpu1_pkgid[0]            :  wOverrideValue[5 ];// pin rjo #6  address = 0x20
      rCurrentValue[6 ] =  wOvEnable_n  [6 ] ? cpu1_pkgid[1]            :  wOverrideValue[6 ];// pin rjo #7  address = 0x24
      rCurrentValue[7 ] =  wOvEnable_n  [7 ] ? cpu1_pkgid[2]            :  wOverrideValue[7 ];// pin rjo #8  address = 0x28
      rCurrentValue[8 ] =  wOvEnable_n  [8 ] ? rjc_jumper               :  wOverrideValue[8 ];// pin rjo #9  address = 0x2C
      rCurrentValue[9 ] =  wOvEnable_n  [9 ] ? force_rec                :  wOverrideValue[9 ];// pin rjo #10 address = 0x30
      rCurrentValue[10] =  wOvEnable_n  [10] ? ttk_spi_en               :  wOverrideValue[10];// pin rjo #11 address = 0x34
      rCurrentValue[11] =  wOvEnable_n  [11] ? perst[0]                 :  wOverrideValue[11];// pin rjo #12 address = 0x38
      rCurrentValue[12] =  wOvEnable_n  [12] ? perst[1]                 :  wOverrideValue[12];// pin rjo #13 address = 0x3C
      rCurrentValue[13] =  wOvEnable_n  [13] ? cpu0_auxpg               :  wOverrideValue[13];// pin rjo #14 address = 0x40
      rCurrentValue[14] =  wOvEnable_n  [14] ? pass_clr                 :  wOverrideValue[14];// pin rjo #15 address = 0x44
      rCurrentValue[15] =  wOvEnable_n  [15] ? asd_en                   :  wOverrideValue[15];// pin rjo #16 address = 0x48
      rCurrentValue[16] =  wOvEnable_n  [16] ? cpu0_sktocc              :  wOverrideValue[16];// pin rjo #17 address = 0x4C
      rCurrentValue[17] =  wOvEnable_n  [17] ? cpu1_sktocc              :  wOverrideValue[17];// pin rjo #18 address = 0x50
      rCurrentValue[18] =  wOvEnable_n  [18] ? ps_en                    :  wOverrideValue[18];// pin rjo #19 address = 0x54
      rCurrentValue[19] =  wOvEnable_n  [19] ? serial_boot              :  wOverrideValue[19];// pin rjo #20 address = 0x58
      rCurrentValue[20] =  wOvEnable_n  [20] ? adr_ext0                 :  wOverrideValue[20];// pin rjo #21 address = 0x5C
      rCurrentValue[21] =  wOvEnable_n  [21] ? adr_ext1                 :  wOverrideValue[21];// pin rjo #22 address = 0x60
      rCurrentValue[22] =  wOvEnable_n  [22] ? cpu0_therm               :  wOverrideValue[22];// pin rjo #23 address = 0x64
      rCurrentValue[23] =  wOvEnable_n  [23] ? cpu1_therm               :  wOverrideValue[23];// pin rjo #24 address = 0x68
      rCurrentValue[24] =  wOvEnable_n  [24] ? cpu0_pltrst_tpm          :  wOverrideValue[24];// pin rjo #25 address = 0x6C
      rCurrentValue[25] =  wOvEnable_n  [25] ? bmc_safs_20              :  wOverrideValue[25];// pin rjo #26 address = 0x70
   end
   //********************************************************************************************

    

   

   assign   wRST_CPU0_RTCRST_PLD_R_N_RJO              =  rCurrentValue    [0 ];// pin rjo #1  address = 0x0C  wOverrideValue
   assign   wFM_BMCINIT_DISABLE_LVC25_N               =  rCurrentValue    [1 ];// pin rjo #2  address = 0x10  wOverrideValue
   assign   wFM_CPU0_PKGID0                           =  rCurrentValue    [2 ];// pin rjo #3  address = 0x14  wOverrideValue
   assign   wFM_CPU0_PKGID1                           =  rCurrentValue    [3 ];// pin rjo #4  address = 0x18  wOverrideValue
   assign   wFM_CPU0_PKGID2                           =  rCurrentValue    [4 ];// pin rjo #5  address = 0x1C  wOverrideValue
   assign   wFM_CPU1_PKGID0                           =  rCurrentValue    [5 ];// pin rjo #6  address = 0x20  wOverrideValue
   assign   wFM_CPU1_PKGID1                           =  rCurrentValue    [6 ];// pin rjo #7  address = 0x24  wOverrideValue
   assign   wFM_CPU1_PKGID2                           =  rCurrentValue    [7 ];// pin rjo #8  address = 0x28  wOverrideValue
   assign   wPFR_DEBUG_JUMPER_RJC_N_IN                =  rCurrentValue    [8 ];// pin rjo #9  address = 0x2C  wOverrideValue
   assign   wPFR_FORCE_RECOVERY_RJC_N_IN              =  rCurrentValue    [9 ];// pin rjo #10 address = 0x30  wOverrideValue
   assign   wFM_TTK_SPI_EN_RJC_N_IN                   =  rCurrentValue    [10];// pin rjo #11 address = 0x34  wOverrideValue
   assign   wFM_RST_PERST_BIT0_LVC25                  =  rCurrentValue    [11];// pin rjo #12 address = 0x38  wOverrideValue
   assign   wFM_RST_PERST_BIT1_LVC25                  =  rCurrentValue    [12];// pin rjo #13 address = 0x3C  wOverrideValue
   assign   PWRGD_CPU0_PLT_AUX_PWRGD_FPGA_LVC18_R     =  rCurrentValue    [13];// pin rjo #14 address = 0x40  wOverrideValue
   assign   wFM_PASSWORD_CLEAR_LVC25_N                =  rCurrentValue    [14];// pin rjo #15 address = 0x44  wOverrideValue
   assign   wFM_ASD_EN_DET_LVC3                       =  rCurrentValue    [15];// pin rjo #16 address = 0x48  wOverrideValue
   assign   wFM_CPU0_SKTOCC_LVT3_PLD_N                =  rCurrentValue    [16];// pin rjo #17 address = 0x4C  wOverrideValue
   assign   wFM_CPU1_SKTOCC_LVT3_PLD_N                =  rCurrentValue    [17];// pin rjo #18 address = 0x50  wOverrideValue
   assign   FM_PS_EN_PLD_R_LVC3                       =  rCurrentValue    [18];// pin rjo #19 address = 0x54  wOverrideValue
   assign   wFM_SERIAL_BOOT                           =  rCurrentValue    [19];// pin rjo #20 address = 0x58  wOverrideValue
   assign   wFM_CPU0_ADR_EXT_TRIGGER_LVC25_N          =  rCurrentValue    [20];// pin rjo #21 address = 0x5C  wOverrideValue
   assign   wFM_CPU1_ADR_EXT_TRIGGER_LVC25_N          =  rCurrentValue    [21];// pin rjo #22 address = 0x60  wOverrideValue
   assign   wH_CPU0_THERMTRIP_FPGA_LVC1_R_N           =  rCurrentValue    [22];// pin rjo #23 address = 0x64  wOverrideValue
   assign   wH_CPU1_THERMTRIP_LVC1_R2_N               =  rCurrentValue    [23];// pin rjo #24 address = 0x68  wOverrideValue
   assign   RST_PLTRST_CPU0_TPM_PLD_LVC18_N           =  rCurrentValue    [24];// pin rjo #25 address = 0x6C  wOverrideValue
   assign   wFM_CPU0_GPIO4_EAF_BMC_SAFS_SEL_LVC1_RJO  =  rCurrentValue    [25];// pin rjo #26 address = 0x70  wOverrideValue


   //flash avmm intf--Flash
   wire         flash_csr_addr;
   wire         flash_csr_read;
   wire [31: 0] flash_csr_writedata;
   wire         flash_csr_write;
   wire [31: 0] flash_csr_readdata;
   wire [31: 0] flash_data_addr;
   wire         flash_data_read;
   wire [31: 0] flash_data_writedata;
   wire         flash_data_write;
   wire [31: 0] flash_data_readdata;
   wire         flash_data_waitrequest;
   wire         flash_data_readdatavalid;
   wire [ 6: 0] flash_data_burstcount;

   //flash avmm intf--RJC
   wire         RJO_flash_csr_addr;
   wire         RJO_flash_csr_read;
   wire [31: 0] RJO_flash_csr_writedata;
   wire         RJO_flash_csr_write;
   wire [31: 0] RJO_flash_csr_readdata;
   wire [31: 0] RJO_flash_data_addr;
   wire         RJO_flash_data_read;
   wire [31: 0] RJO_flash_data_writedata;
   wire         RJO_flash_data_write;
   wire [31: 0] RJO_flash_data_readdata;
   wire         RJO_flash_data_waitrequest;
   wire         RJO_flash_data_readdatavalid;
   wire [ 6: 0] RJO_flash_data_burstcount;


   // Mul that do redirection 2 master(PFR and RJO data) to memory flash slave.
   Flash_avmm_mux_2to1 Flash_avmm_mux_2to1_inst
     (
      .clk                        ( wClk_20M                      ),
      .rst_n                      ( Reset_N                       ),
      .RSU_FlashBusy              ( RSU_FlashBusy                       ),
      .slv_csr_addr               ( flash_csr_addr                      ),
      .slv_csr_read               ( flash_csr_read                      ),
      .slv_csr_writedata          ( flash_csr_writedata                 ),
      .slv_csr_write              ( flash_csr_write                     ),
      .slv_csr_readdata           ( flash_csr_readdata                  ),
      .slv_data_addr              ( flash_data_addr                     ),
      .slv_data_read              ( flash_data_read                     ),
      .slv_data_writedata         ( flash_data_writedata                ),
      .slv_data_write             ( flash_data_write                    ),
      .slv_data_readdata          ( flash_data_readdata                 ),
      .slv_data_waitrequest       ( flash_data_waitrequest              ),
      .slv_data_readdatavalid     ( flash_data_readdatavalid            ),
      .slv_data_burstcount        ( flash_data_burstcount               ),

      .master1_csr_addr           ( RSU_flash_csr_addr                  ),
      .master1_csr_read           ( RSU_flash_csr_read                  ),
      .master1_csr_writedata      ( RSU_flash_csr_writedata             ),
      .master1_csr_write          ( RSU_flash_csr_write                 ),
      .master1_csr_readdata       ( RSU_flash_csr_readdata              ),
      .master1_data_addr          ( RSU_flash_data_addr                 ),
      .master1_data_read          ( RSU_flash_data_read                 ),
      .master1_data_writedata     ( RSU_flash_data_writedata            ),
      .master1_data_write         ( RSU_flash_data_write                ),
      .master1_data_readdata      ( RSU_flash_data_readdata             ),
      .master1_data_waitrequest   ( RSU_flash_data_waitrequest          ),
      .master1_data_readdatavalid ( RSU_flash_data_readdatavalid        ),
      .master1_data_burstcount    ( RSU_flash_data_burstcount           ),

      .master2_csr_addr           ( RJO_flash_csr_addr                  ),
      .master2_csr_read           ( RJO_flash_csr_read                  ),
      .master2_csr_writedata      ( RJO_flash_csr_writedata             ),
      .master2_csr_write          ( RJO_flash_csr_write                 ),
      .master2_csr_readdata       ( RJO_flash_csr_readdata              ),
      .master2_data_addr          ( RJO_flash_data_addr                 ),
      .master2_data_read          ( RJO_flash_data_read                 ),
      .master2_data_writedata     ( RJO_flash_data_writedata            ),
      .master2_data_write         ( RJO_flash_data_write                ),
      .master2_data_readdata      ( RJO_flash_data_readdata             ),
      .master2_data_waitrequest   ( RJO_flash_data_waitrequest          ),
      .master2_data_readdatavalid ( RJO_flash_data_readdatavalid        ),
      .master2_data_burstcount    ( RJO_flash_data_burstcount           )
    );

    Pmode Pmode_inst(
        .CLOCK_50M       (wClk_50M),                             //master clock for this block
        .RESET_N         (wRst_n),                              //master reset, must be de-asserted synchronously with clock, generated by locked sigal of main pll
        .POD_PRESENT_N   (FM_DBP_POD_PRSNT_N),                  
        .CPU_PWRGD       (PWRGD_CPU0_FPGA_LVC1),                
        .S0_PWR_OK       (PWRGD_CPU0_S0_PWROK_LVC1_R),          
        .PLTRST          (RST_PLTRST_CPU0_PLD_LVC18_N),         
        .Silicon_GLB_RST (FM_CPU0_GLB_RST_WARN_FPGA_LVC18_N_R),
        .PMODE           (DBP_PMODE_R_LVC18)
    );

   assign H_CPU0_MEMHOT_IN_LVC1_R_N = wPWRGD_PVNN_MAIN_CPU0_FF ? wH_CPU0_MEMHOT_IN_LVC1_R_N : 1'bZ;
   assign H_CPU1_MEMHOT_IN_LVC1_R_N = wPWRGD_PVNN_MAIN_CPU1_FF ? wH_CPU1_MEMHOT_IN_LVC1_R_N : 1'bZ;
   assign H_CPU0_PROCHOT_LVC1_R_N   = wPWRGD_PVNN_MAIN_CPU0_FF ? wH_CPU0_PROCHOT_LVC1_R_N   : 1'bZ;
   assign H_CPU1_PROCHOT_LVC1_R_N   = wPWRGD_PVNN_MAIN_CPU1_FF ? wH_CPU1_PROCHOT_LVC1_R_N   : 1'bZ;


   InputsSyncWithDefault # (
   .SIZE       ( 7 ),
   .DEFAULT_OUT( 7'b0101100)
) InputsSyncWithDefault_ESPI (
   .i_Clk  ( wClk_100M ),
   .i_Rst_n( wRst_n ),
   .i_vSync({
              wFM_PCIE_FV_BIF_EN,
              wCPU_IRQ_NMI_ESPI,
              wPWRGD_CPU0_PLT_AUX_PWRGD_FPGA_LVC18_R,
              wCpu0IntrPrsnt_n,
              wCpu1IntrPrsnt_n,
              wCpu0IntrTypeABn,
              wCpu1IntrTypeABn
             }),
   .o_vSync({
              wFmPcieFvBifEn_SyncESPI,
              wCpuIrqNmiEspi_SyncESPI,
              wPwrgdCpu0PltAuxPwrgdFpga_SyncESPI,
              wCpu0IntrPrsnt_n_SyncESPI,
              wCpu1IntrPrsnt_n_SyncESPI,
              wCpu0IntrTypeABn_SyncESPI,
              wCpu1IntrTypeABn_SyncESPI
            })
   );

endmodule // mainfpga_top

